Описание
The SMART SAM G53 is a series of Flash microcontrollers based on the high-performance 32-bit ARM Cortex -M4 RISC processor. It operates at a maximum speed of 48 MHz and features up to 512 Kbytes of Flash and 96 Kbytes of SRAM. The peripheral set includes one USART, two UARTs, three I²C-bus interfaces (TWI), up to two SPIs, two three-channel general-purpose 16-bit timers, two I²S controllers with two-way, one-channel pulse density modulation, one realtime timer (RTT) and one 8-channel 12-bit ADC. The SMART SAM G53 devices have two software-selectable low-power modes: Sleep and Wait. In Sleep mode, the processor is stopped while all other functions can be kept running. In Wait mode, all clocks and functions are stopped but some peripherals can be configured to wake up the system based on events, including partial asynchronous wake-up (SleepWalking). The Event System allows peripherals to receive, react to and send events in Active and Sleep modes without processor intervention. A general-purpose microcontroller with the best ratio in terms of reduced power consumption, processing power and peripheral set, the SAM G53 series sustains a wide range of applications including consumer, industrial control, and PC peripherals. The device operates from 1.62V to 3.6V and is available in a 49-ball WLCSP package and a 100-pin LQFP package.
- Core ?
- ARM Cortex-M4 up to 48 MHz
- Memory Protection Unit (MPU) ?
- DSP Instructions ?
- Floating Point Unit (FPU) ?
- Thumb®-2 instruction set
- Memories ?
- 512 Kbytes embedded Flash ?
- 96 Kbytes embedded SRAM
- System ?
- Embedded voltage regulator for single-supply operation ?
- Power-on reset (POR) and Watchdog for safe operation ?
- Quartz or ceramic resonator oscillators: 3 to 20 MHz with clock failure detection and 32.768 kHz for RTT or device clock ?
- High-precision 8/16/24 MHz factory-trimmed internal RC oscillator. In-application trimming access for frequency adjustment ?
- Slow clock internal RC oscillator as permanent Low-power mode device clock ?
- PLL range from 24 MHz to 48 MHz for device clock ?
- 28 peripheral DMA (PDC) channels ?
- 256-bit General-Purpose Registers (GPBR) ?
- 16 external interrupt lines
- Power consumption in Active mode ?
- 102 µA/MHz running Fibonacci in SRAM
- Low power modes (typical value)
- Wait mode down to 8 µA ?
- Wake-up time less than 5 µs ?
- Asynchronous partial wake-up (SleepWalking™) on UART and TWI
- Peripherals ?
- One USART with SPI mode ?
- Two Inter-IC Sound Controllers (I²S) ?
- Two-way one-channel Pulse Density Modulation (PDM) (interfaces up to two microphones in PDM mode) ?
- Two UARTs ?
- Three Two-Wire Interface (TWI) modules featuring two TWI masters and one high-speed TWI slave ?
- One fast SPI at up to 24Mbit/s ?
- Two three-channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes ?
- One 32-bit Real-Time Timer (RTT)
- I/O
- Up to 38 controllable I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die series resistor termination. Individually programmable open-drain, pull-up and pull-down resistor and synchronous output
- Analog
- One 8-channel ADC, resolution up to 12 bits, sampling rate up to 800 kSps
- Package
- 49-ball WLCSP ?
- 100-pin LQFP, 14 x 14 mm, pitch 0.5 mm
- Temperature operating range
- Industrial (-40°C to +85°C)
