Description
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, Two 12-bit ADCs (three S/H circuits, double data registers, amplifier, comparator), one 10-bit ADC, simultaneous sampling on 7 channels using three ADCs, 100 MHz PWM (2 three-phase complementary channels + 4 single-phase complementary channels or 3 three-phase complementary channels + 1 single-phase complementary channel).
32-bit RX CPU core Max. operating frequency: 100 MHz Capable of 165 DMIPS in operation at 100 MHz Single precision 32-bit IEEE-754 floating point Two types of multiply-and-accumulation unit (between memories and between registers) 32-bit multiplier (fastest instruction execution takes one CPU clock cycle) Divider (fastest instruction execution takes two CPU clock cycles) Fast interrupt CISC Harvard architecture with 5-stage pipeline Variable-length instructions: Ultra-compact code Supports the memory protection unit (MPU) Two types of debugging interfaces: JTAG and FINE (two-line) Low-power design and architecture Single 3.3-V supply or single 5-V supply; 3.3-V products can be used with a 5-V analog power supply Four low-power modes On-chip main flash memory, no wait states 100-MHz operation, 10-ns read cycle (no wait states) 256 Kbytes User code is programmable by USB, SCI, or JTAG On-chip data flash memory Programming/erasing as background operations (BGOs) On-chip SRAM, no wait states 24 Kbytes For instructions and operands DMA DMA: Incorporates four channels DTC: A single unit can handle transfer on multiple channels Reset and supply management Power-on reset (POR) Low voltage detection (LVD) with voltage settings Package : LQFP
