Description
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash memory, various communications interfaces including Ethernet MAC, full-speed USB 2.0 host/function/OTG interface, CAN, 10- & 12-bit A/D converters, RTC.
32-bit RX CPU core Max. operating frequency: 100 MHz Capable of 165 DMIPS in operation at 100 MHz Single precision 32-bit IEEE-754 floating point Two types of multiply-and-accumulation unit (between memories and between registers) 32-bit multiplier (fastest instruction execution takes one CPU clock cycle) Divider (fastest instruction execution takes two CPU clock cycles) Fast interrupt CISC Harvard architecture with 5-stage pipeline Variable-length instructions: Ultra-compact code Supports the memory protection unit (MPU) JTAG and FINE (two-line) debugging interfaces Low-power design and architecture Operation from a single 2.7- to 3.6-V supply Low power consumption: A product that supports all peripheral functions draws only 500 µA/MHz. RTC is capable of operation from a dedicated power supply (min. operating voltage: 2.3 V). Four low-power modes On-chip main flash memory, no wait states Supports ROM-less versions and versions with up to 2 Mbytes of ROM 100-MHz operation, 10-ns read cycle (no wait states) 768-Kbyte capacities User code is programmable by on-board or off-board programming On-chip data flash memory ROM-less or 32 Kbytes of ROM (reprogrammable up to 100,000 times) Programming/erasing as background operations (BGOs) On-chip SRAM, no wait states 128 Kbytes of SRAM For instructions and operands Can provide backup on deep software standby Package : LFBGA
