Description
MCU 32-Bit RX62N RX CISC 384KB Flash 3.3V 144-Pin LQFP Tray
32-bit RX CPU Core Delivers 165 DMIPS at a maximum operating frequency of 100 MHz Single Precision 32-bit IEEE-754 Floating Point Accumulator: 32 × 32 to 64-bit result, one instruction Mult/Divide Unit, 32 × 32 Multiply in one CPU clock for multiple instructions Interrupt response in as few as 5 CPU clock cycles CISC-Harvard Architecture with 5-stage pipeline Variable length instructions, ultra compact code Supports the Memory Protection Unit (MPU) Background JTAG debug plus high-speed trace Low Power Design and Architecture 2.7V to 3.6V operation from a single supply 480 µA/MHz Run Mode with all peripherals on Deep Software Standby Mode with RTC Four low power modes Main Flash Memory, no Wait-State 100 MHz operation, 10 nsec read cycle No wait states for read at full CPU speed 384 KByte size options For Instructions or Operands Programming from USB, SCI, JTAG, user code Data Flash Memory 32 KBytes with 30K Erase Cycles Background Erase/Program does not stall CPU SRAM, no Wait-State 64 KByte size options For Operands or Instructions Back-up retention in Deep Software Standby Mode DMA Four fully programmable internal DMA channels Two EXDMA channels for external-to-external transfers Data Transfer Controller (DTC) Reset and Supply Management Power-On Reset (POR) monitor/generator Low Voltage Detect (LVD) with precision setting System Clocking with Clock Monitoring External crystal, 8 MHz to 14 MHz to Internal PLL Package : LQFP
