Description
32-MHz 32-bit RX MCUs, 49 DMIPS, up to 256-KB flash memory, 12-bit A/D, ELC, MPC, IrDA, RTC, up to 7 comms channels; incorporating functions for IEC60730 compliance
- 32-bit RX CPU core
- o Max. operating frequency: 32 MHz
- o Capable of 49 DMIPS in operation at 32 MHz
- o Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations
- o Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)
- o Fast interrupt
- o CISC Harvard architecture with 5-stage pipeline
- o Variable-length instructions, ultra-compact code
- o On-chip debugging circuit
- Low-power design and architecture
- o Operation from a single 1.62-V to 5.5-V supply
- o 1.62-V operation available (at up to 8 MHz)
- o Three low-power modes
- On-chip flash memory for code, no wait states
- o 32-MHz operation, 31.25-ns read cycle
- o No wait states for reading at full CPU speed
- o Up to 256-Kbyte capacity
- o User code programmable via the SCI
- o Programmable at 1.62 V
- o For instructions and operands
- On-chip data flash memory
- o 8 Kbytes (Number of times of reprogramming: 100,000)
- o Erasing and programming impose no load on the CPU.
- On-chip SRAM, no wait states
- o Up to 16-Kbyte size capacity
- DMA
- o DMAC: Incorporates four channels
- o DTC: Four transfer modes
- ELC
- o Module operation can be initiated by event signals without going through interrupts.
- o Modules can operate while the CPU is sleeping.
- Reset and supply management
- o Seven types of reset, including the power-on reset (POR)
- o Low voltage detection (LVD) with voltage settings
- Clock functions
- o Frequency of external clock: Up to 20 MHz
- o Frequency of the oscillator for sub-clock generation: 32.768 kHz
- o On-chip low- and high-speed oscillators, dedicated on chip low-speed oscillator for the IWDT
- o Generation of a dedicated 32.768-kHz clock for the RTC
- o Clock frequency accuracy measurement circuit (CAC)
- Real-time clock
- o Adjustment functions (30 seconds, leap year, and error)
- o Year and month display or 32-bit second display (binary counter) is selectable
- Independent watchdog timer
- o 125-kHz on-chip oscillator produces a dedicated clock signal to drive IWDT operation.
- Useful functions for IEC60730 compliance
- o Self-diagnostic and disconnection-detection assistance functions for the A/D converter, clock-frequency accuracy-measurement circuit, independent watchdog timer, functions to assist in RAM testing, etc.
- Up to seven communications channels
- o SCI with many useful functions (up to five channels) Asynchronous mode, clock synchronous mode, smart card interface mode
- o IrDA Interface (one channel, in cooperation with the SCI5)
- o I2C bus interface: Transfer at up to 400 kbps, capable of SMBus operation (one channel)
- o RSPI (one channel)
- Up to 14 extended-function timers
- o 16-bit MTU: input capture, output capture, complementary PWM output, phase counting mode (six channels)
- o 8-bit TMR (four channels)
- o 16-bit compare-match timers (four channels)
- 12-bit A/D converter
- o Capable of conversion within 1.56 µs
- o Self-diagnostic function and analog input disconnection detection assistance function
- Analog comparator
- General I/O ports
- o 5-V tolerant, open drain, input pull-up, switching of driving ability
- MPC
- o Multiple locations are selectable for I/O pins of peripheral functions
- Operating temp. range
- o -40°C to +85°C
- ROM, RAM, and E2 Data Flash capacity 64 Kbytes/8 Kbytes/8 Kbytes
