Description
RX210 Flash MCUs bring new levels of capability and performance to ultra-low-power, low-voltage embedded-system applications. Based on the fast 32-bit RX CPU core, RX210 chips are the first members of the RX200 series of middle-range products.
- 32-bit RX CPU Core
- Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz
- Accumulator handles 64-bit results (for a single instruction) from 32- x 32-bit operations
- Multiplication and division unit handles 32- x 32-bit operations (multiplication instructions take one CPU clock cycle)
- Fast interrupt
- CISC Harvard architecture with 5-stage pipeline
- Variable-length instructions, ultra-compact code
- On-chip debugging circuit
- Operation from a single 1.62- to 5.5-V supply
- 1.62-V operation available (at up to 20 MHz)
- Deep software standby mode with RTC remaining usable
- Four low-power modes
- 50-MHz operation, 20-ns read cycle
- No wait states for reading at full CPU speed
- 128- to 512-Kbyte capacities
- User code programmable via the SCI
- Programmable at 1.62 V
- Eight Kbytes
- Erasing and programming impose no load on the CPU.
- 20- to 64-Kbyte size capacities
- DMACA: Incorporates four channels
- DTC: Four transfer modes
- Module operation can be initiated by event signals without going through interrupts
- Modules can operate while the CPU is sleeping.
- Nine types of reset, including the power-on reset (POR)
- Low voltage detection (LVD) with voltage settings
- Frequency of external clock: Up to 20 MHz
- Frequency of the oscillator for sub-clock generation: 32.768 kHz
- PLL circuit input: 4 to 12.5 MHz
- On-chip low- and high-speed oscillators, dedicated on chip low-speed oscillator for the IWDT
- Generation of a dedicated 32.768-kHz clock for the RTC
- Clock frequency accuracy measurement circuit (CAC)
- Adjustment functions (30 seconds, leap year, and error)
- Time capture function
- Time capture on event-signal input through external pins
- RTC capable of initiating return from deep software standby mode
- 125-kHz on-chip low-speed oscillator produces a dedicated clock signal to drive IWDT operation
- Adjustment functions (30 seconds, leap year, and error)
- SCI with many useful functions (up to seven interfaces)
- Asynchronous mode, clock synchronous mode, smart card interface
- I2C bus interface: Transfer at up to 1 Mbps, capable of SMBus operation (1 interface)
- RSPI
- Four CS areas (4 x 16 Mbytes)
- 8- or 16-bit bus space is selectable per area
- 16-bit MTU2: input capture, output capture, complementary PWM output, phase counting mode (6 channels)
- 8-bit TMR (4 channels)
- 16-bit compare-match timers (4 channels)
- Capable of conversion within 1 µs
- Sample-and-hold circuits (for three channels)
- Three-channel synchronized sampling available
- Self-diagnostic function and analog input disconnection detection assistance function
- 5-V tolerant, open drain, input pull-up, switching of driving ability
- ROM, RAM, and E2 Data Flash capacity 64 Kbytes/12 Kbytes/8 Kbytes
- Chip version B
- Operating temperature (–40 to +85°C)
