Описание
The PXD10 family of chips is designed to enable the development of industrial HMI applications by providing a single-chip solution capable of hosting real-time applications and driving a TFT display directly using an on-chip color TFT display controller. PXD10 chips incorporate a cost-efficient host processor core compliant with the Power Architecture embedded category. The processor is 100% user-mode compatible with the Power Architecture and capitalizes on the available development infrastructure of current Power Architecture devices with full support from available software drivers, operating systems and configuration code to assist with users" implementations. Offering high performance processing at speeds up to 64 MHz, the PXD10 family is optimized for low power consumption and supports a range of on-chip SRAM and internal flash memory sizes. The version with 1 MB of flash memory (PXD1010) features 160 KB of on-chip graphics SRAM.
- Single issue, 32-bit Power Architecture technology compliant CPU core complex (e200z0h)
- Compatible with Power Architecture instruction set
- Includes variable length encoding (VLE) instruction set for smaller code size footprint; with the encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over conventional Book E compliant code
- On-chip ECC flash memory with flash controller
- As much as 1 MB primary flash – two 512 KB modules with prefetch buffer and 128-bit data access port-
- 64 KB data flash – separate 4 x 16 KB flash block for EEPROM emulation with prefetch buffer and 128-bit data access port
- As much as 48 KB on-chip ECC SRAM with SRAM controller
- As much as 160 KB on-chip non-ECC graphics SRAM with SRAM controller
- Memory Protection Unit (MPU) with as many as 12 region descriptors and 32-byte region granularity to provide basic memory access permission
- Interrupt Controller (INTC) with as many as 127 peripheral interrupt sources and eight software interrupts
- Two Frequency-Modulated Phase-Locked Loops (FMPLLs)
- Primary FMPLL provides a 64 MHz system clock
- Auxiliary FMPLL is available for use as an alternate, modulated or non-modulated clock source to eMIOS modules and as alternate clock to the DCU for pixel clock generation
- Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus masters (AMBA 2.0 v6 AHB)
- 16-channel Enhanced Direct Memory Access controller (eDMA) with multiple transfer request sources using a DMA channel multiplexer
- Boot Assist Module (BAM) supports internal flash programming via a serial link (FlexCAN or LINFlex)
- Display Control Unit to drive TFT LCD displays
- Includes processing of as many as four planes that can be blended together
- Offers a direct unbuffered hardware bit-blitter of as many as 16 software-configurable dynamic layers in order to drastically minimize graphic memory requirements and provide fast animations
- Programmable display resolutions are available up to WVGA
- Parallel Data Interface (PDI) for digital video input
- LCD segment driver module with two software programmable configurations:
- As many as 40 frontplane drivers and four backplane drivers
- As many as 38 frontplane drivers and six backplane drivers
- Stepper Motor Controller (SMC) module with high-current drivers for as many as six stepper motors driven in full dual H-Bridge configuration including full diagnostics for short circuit detection
- Stepper motor return-to-zero and stall detection module
- Sound generation and playback utilizing PWM channels and eDMA; supports monotonic and polyphonic sound
- 24 eMIOS channels providing as many as 16 PWM and 24 input capture / output compare channels
- 10-bit Analog-to-Digital Converter (ADC)
- Maximum conversion time of 1 µs
- As many as 16 internal channels, expandable to 23 via external multiplexing
- As many as two Serial Peripheral Interface (DSPI) modules for full-duplex, synchronous, communications with external devices (extendable to include up to 8 multiplexed external channels)
- QuadSPI serial flash memory controller supporting single, dual and quad modes of operation to interface to external serial flash memory. QuadSPI can be configured to function as another DSPI module.
- Two full CAN 2.0B controllers with 64 configurable buffers each; bit rate programmable as fast as 1 Mbit/s
