Описание
PIC32MX675F512L is 32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Graphics Interface, USB, CAN, and Ethernet The MIPS32 M4K Processor core is the heart of the PIC32MX5XX/6XX/7XX family processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations The MIPS M4K processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e Support Enhanced JTAG (EJTAG) Controller The MIPS M4K processor core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autono- mous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. One addi- tional register file shadow set (containing thirty-two reg- isters) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes: 32-bit adder used for calculating the data address Address unit for calculating the next instruction address Logic for branch determination and branch target address calculation Load aligner Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results Leading Zero/One detect unit for implementing the CLZ and CLO instructions Arithmetic Logic Unit (ALU) for performing bit-wise logical operations Shifter and store aligner MIPS M4K processor core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multi- ply and divide operations. This pipeline operates in par- allel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU opera- tions to be partially masked by system stalls and/or other integer unit instructions. The high-performance MDU consists of a 32×16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (‘32’ of 32×16) represents the rs operand. The second number (‘16’ of 32×16) represents the rt operand. The PIC32 core only checks t he value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16×16 and 32×16 operations pass through the multiplier once. A 32×32 operation passes through the multiplier twice. The MDU supports execution of one 16×16 or 32×16 multiply operation every clock cycle; 32×32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32×32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU Divide operations are implemented with a simple 1 bit per clock iterative algorith m. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16 bit wide rs , 15 iterations are skipped and for a 24 bit wide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed.
- Core: 80 MHz/105 DMIPS MIPS32® M4K®
- MIPS16e® mode for up to 40% smaller code size
- Code-efficient (C and Assembly) architecture
- Single-cycle (MAC) 32×16 and two-cycle 32×32 multiply
- Clock Management
- 0.9% internal oscillator
- Programmable PLLs and oscillator clock sources
- Fail-Safe Clock Monitor (FSCM)
- Independent Watchdog Timer
- Fast wake-up and start-up
- Power Management
- Low-power management modes (Sleep and Idle)
- Integrated Power-on Reset, Brown-out Reset
- 0.5 mA/MHz dynamic current (typical)
- 41 µA IPD current (typical)
- Graphics Features
- External graphics interface with up to 34 Parallel Master Port (PMP) pins:
- Interface to external graphics controller
- Capable of driving LCD directly with DMA and internal or external memory
- Analog Features
- ADC Module:
- 10-bit 1 Msps rate with one Sample and Hold (S&H)
- 16 analog inputs
- Can operate during Sleep mode
- Flexible and independent ADC trigger sources
- Comparators:
- Two dual-input Comparator modules
- Programmable references with 32 voltage points Timers/Output Compare/Input Capture
- Five General Purpose Timers:
- Five 16-bit and up to two 32-bit Timers/Counters
- Five Output Compare (OC) modules
- Five Input Capture (IC) modules
- Real-Time Clock and Calendar (RTCC) module Communication Interfaces
- USB 2.0-compliant Full-Speed OTG controller
- 10/100 Mbps Ethernet MAC with MII and RMII interface
- CAN module:
- 2.0B Active with DeviceNet™ addressing support
- Six UART modules (20 Mbps):
- Supports LIN 1.2 protocols and IrDA® support
- Up to four 4-wire SPI modules (25 Mbps)
- Up to five I2C modules (up to 1 Mbaud) with SMBus support
- Parallel Master Port (PMP) Direct Memory Access (DMA)
- Up to eight channels of hardware DMA with automatic data size detection
- 32-bit Programmable Cyclic Redundancy Check (CRC)
- Six additional channels dedicated to USB, Ethernet and CAN modules Input/Output
- 15 mA or 10 mA source/sink for standard VOH/V OL and up to 22 mA for non-standard VOH1
- 5V-tolerant pins
- Selectable open drain and pull-ups
- External interrupts Qualification and Class B Support
- AEC-Q100 REVG (Grade 2 -40°C to +105°C) planned
- Class B Safety Library, IEC 60730 Debugger Development Support
- In-circuit and in-application programming
- 4-wire MIPS® Enhanced JTAG interface
- Unlimited program and six complex data breakpoints
- IEEE 1149.2-compatible (JTAG) boundary scan
