Описание
PIC32MX575F256L is High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers The MIPS32 M4K Processor core is the heart of the PIC32MX5XX/6XX/7XX family processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations The MIPS M4K processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are in cluded with the core: Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e Support Enhanced JTAG (EJTAG) Controller The MIPS M4K processor core execution unit imple- ments a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autono- mous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. One addi- tional register file shadow set (containing thirty-two reg- isters) is added to minimize context switching overhead during interrupt/exception proc essing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline The execution unit includes: 32-bit adder used for calculating the data address Address unit for calculating the next instruction address Logic for branch determination and branch target address calculation Load aligner Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results Leading Zero/One detect unit for implementing the CLZ and CLO instructions Arithmetic Logic Unit (ALU) for performing bitwise logical operations Shifter and store aligner MIPS M4K processor core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multi- ply and divide operations. This pipeline operates in par- allel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU opera- tions to be partially masked by system stalls and/or other integer unit instructions The high-performance MDU consists of a 32×16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (‘32’ of 32×16) represents the rs operand. The second number (‘16’ of 32×16) represents the rt operand. The PIC32 core only checks the value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16×16 and 32×16 operations pass through the multiplier once. A 32×32 operation passes through the multiplier twice The MDU supports execution of one 16×16 or 32×16 multiply operation every clock cycle; 32×32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32×32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU Divide operations are implemented with a simple 1 bit per clock iterative algorith m. An early-in detection checks the sign extension of the dividend (rs) operand.If rs is 8 bits wide, 23 iterations are skipped. For a 16 bit wide rs, 15 iterations are skipped and for a 24 bit wide rs,7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed
- High-Performance 32-bit RISC CPU:
- MIPS32® M4K® 32-bit core with 5-stage pipeline
- 80 MHz maximum frequency
- 1.56 DMIPS/MHz (Dhrystone 2.1) performance at zero Wait state Flash access
- Single-cycle multiply and high-performance divide unit
- MIPS16e® mode for up to 40% smaller code size
- Two sets of 32 core register files (32-bit) to reduce interrupt latency
- Prefetch Cache module to speed execution from Flash Microcontroller Features:
- Operating voltage range of 2.3V to 3.6V
- 64K to 512K Flash memory (plus an additional 12 KB of Boot Flash)
- 16K to 128K SRAM memory
- Pin-compatible with most PIC24/dsPIC® DSC devices
- Multiple power management modes
- Multiple interrupt vectors with individually programmable priority
- Fail-Safe Clock Monitor mode
- Configurable Watchdog Timer with on-chip Low-Power RC oscillator for reliable operation
- Peripheral Features:
- Atomic SET, CLEAR and INVERT operation on select peripheral registers
- Up to 8-channels of hard ware DMA with automatic data size detection
- USB 2.0-compliant full-speed device and On-The-Go (OTG) controller:
- Dedicated DMA channels
- 10/100 Mbps Ethernet MAC with MII and RMII interface:
- Dedicated DMA channels
- CAN module:
- 2.0B Active with DeviceNet™ addressing support
- Dedicated DMA channels
- 3 MHz to 25 MHz crystal oscillator
- Internal 8 MHz and 32 kHz oscillators
- Six UART modules with:
- RS-232, RS-485 and LIN support -IrDA® with on-chip hardware encoder and decoder
- Up to four SPI modules
- Up to five I2C™ modules
- Separate PLLs for CPU and USB clocks
- Parallel Master and Slave Port (PMP/PSP) with 8-bit and 16-bit data, and up to 16 address lines
- Hardware Real-Time Clock and Calendar (RTCC)
- Five 16-bit Timers/Counters (two 16-bit pairs combine to create two 32-bit timers)
- Five Capture inputs
- Five Compare/PWM outputs
- Five external interrupt pins
- High-speed I/O pins capable of toggling at up to 80 MHz
- High-current sink/source (18 mA/18 mA) on all I/O pins
- Configurable open-drain output on digital I/O pins
- Debug Features:
- Two programming and debugging Interfaces:
- 2-wire interface with unintrusive access and real-time data exchange with application
- 4-wire MIPS® standard enhanced Joint Test Action Group (JTAG) interface
- Unintrusive hardware-based instruction trace
- IEEE Standard 1149.2 compatible (JTAG) boundary scan
- Analog Features:
- Up to 16-channel, 10-bit Analog-to-Digital Converter:
- 1 Msps conversion rate
- Conversion available during Sleep and Idle
- Two Analog Comparators
