MCU 32-Bit MB9B320L ARM Cortex M3 RISC 288KB Flash 3.3V/5V 64-Pin LQFP, MB9BF324LPMC1-G-JNE2, Rochester Electronics

Описание

The MB9BF324L is a highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, DACs and Communication Interfaces (USB, UART, CSIO, I2C, LIN).

• 32-bit ARM Cortex-M3 Core
• Processor version: r2p1
• Up to 72 MHz Frequency Operation
• Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
• 24-bit System timer (Sys Tick): System timer for OS task management

On-chip Memories
[Flash memory]

• Dual operation Flash memory
• Main area: Up to 256 Kbytes
• Work area: 32 Kbytes
• Read cycle: 0 wait-cycle
• Security function for code protection

[SRAM]
This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus or D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.

• SRAM0: Up to 16 Kbytes
• SRAM1: Up to 16 Kbytes

USB Interface
The USB interface is composed of Function and Host. [USB function]

• USB2.0 Full-Speed supported
• Max 6 EndPoint supported
• EndPoint 0 is control transfer
• EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer
• EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer
• EndPoint 1 to 5 are comprised of Double Buffers. [USB host]
• USB2.0 Full/Low-speed supported
• Bulk-transfer, interrupt-transfer and Isochronous-transfer support
• USB Device connected/dis-connected automatic detection
• Automatic processing of the IN/OUT token handshake packet
• Max 256-byte packet-length supported
• Wake-up function supported ,
• Multi-function Serial Interface (Max 8channels)
• 4 channels with 16steps -9-bit FIFO (ch.0/1/3/4), 4 channels without FIFO (ch.2/5/6/7)
• Operation mode is selectable from the followings for each channel.
• UART
• CSIO
• LIN
• I2C

[UART]

• Full duplex double buffer
• Selection with or without parity supported
• Built-in dedicated baud rate generator
• External clock available as a serial clock
• Hardware Flow control : Automatically control the transmission/reception by CTS/RTS (only ch.4)
• Various error detection functions available (parity errors, framing errors, and overrun errors)

[CSIO]

• Full duplex double buffer
• Built-in dedicated baud rate generator
• Overrun error detection function available [LIN]
• LIN protocol Rev.2.1 supported
• Full duplex double buffer
• Master/Slave mode supported
• LIN break field generation (can be changed to 13 to 16-bit length)
• DMA Controller (8channels) The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.
• 8 independently configured and operated channels
• Transfer can be started by software or request from the built-in peripherals
• Transfer address area: 32-bit (4 Gbytes)
• Transfer mode: Block transfer/Burst transfer/Demand transfer
• Transfer data type: byte/half-word/word
• Transfer block count: 1 to 16
• Number of transfers: 1 to 65536

A/D Converter(Max 26 channels) [12-bit A/D Converter]

• Successive Approximation type
• Built-in 2units
• Conversion time: 0.8 us @ 5V
• Priority conversion available (priority at 2levels)
• Scanning conversion mode
• Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps)
• D/A Converter (Max 2channels)
• R-2R type
• 10-bit resolution ,

Base Timer (Max 8channels) Operation mode is selectable from the followings for each channel.

• 16-bit PWM timer
• 16-bit PPG timer
• 16/32-bit reload timer
• 16/32-bit PWC timer