Описание
The MB9BF216S is a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs, and Communication Interfaces (USB, UART, CSIO, I2C, LIN, Ethernet-MAC).
- 32-bit ARM Cortex-M3 Core
- Processor version: r2p1
- Up to 144MHz Frequency Operation
- Memory Protection Unit (MPU): improves the reliability of an embedded system
- Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
- 24-bit System timer (Sys Tick): System timer for OS task management
- On-chip Memories [Flash memory] These series are based on two independent on-chip Flash memories.
- MainFlash
- Up to 512Kbyte
- Built-in Flash Accelerator System with 16Kbyte trace buffer memory
- The read access to Flash memory can be achieved without wait cycle up to operation frequency of 72MHz. Even at the operation frequency more than 72MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System.
- Security function for code protection
- WorkFlash
- 32Kbyte
- Read cycle
- 4wait-cycle: the operation frequency more than 72MHz
- 2wait-cycle: the operation frequency more than 40MHz, and to 72MHz
- 0wait-cycle: the operation frequency to 40MHz
- Security function is shared with code protection [SRAM] This Series contain a total of up to 64Kbyte on-chip SRAM memories. This is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus or D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
- SRAM0: Up to 32 Kbyte
- SRAM1: Up to 32 Kbyte
- External Bus Interface
- Supports SRAM, NOR and NAND Flash device
- Up to 8 chip selects
- 8/16-bit Data width
- Up to 25-bit Address bit
- Supports Address/Data multiplex
- Supports external RDY input , Multi-function Serial Interface (Max 8channels)
- 4 channels with 16-byte FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)
- Operation mode is selectable from the followings for each channel.
- UART
- CSIO
- LIN
- I2C[UART]
- Full-duplex double buffer
- Selection with or without parity supported
- Built-in dedicated baud rate generator
- External clock available as a serial clock
- Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)
- Various error detect functions available (parity errors, framing errors, and overrun errors) [CSIO]
- Full-duplex double buffer
- Built-in dedicated baud rate generator
- Overrun error detect function available [LIN]
- LIN protocol Rev.2.1 supported
- Full-duplex double buffer
- Master/Slave mode supported
- LIN break field generate (can be changed 13 to 16-bit length)
- LIN break delimiter generate (can be changed 1 to 4-bit length)
- Various error detect functions available (parity errors, framing errors, and overrun errors) [I2C] Standard mode (Max 100kbps) / High-speed mode (Max 400kbps) supported
- DMA Controller (8channels) DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
- 8 independently configured and operated channels
- Transfer can be started by software or request from the built-in peripherals
- Transfer address area: 32bit (4Gbyte)
- Transfer mode: Block transfer/Burst transfer/Demand transfer
- Transfer data type: byte/half-word/word
- Transfer block count: 1 to 16
- Number of transfers: 1 to 65536
- A/D Converter (Max 16channels) [12-bit A/D Converter]
