Описание
The AT91SAM9R64 device is based on the integration of an ARM926EJ-S processor with a large fast SRAM and a wide range of peripherals. The AT91SAM9R64 embeds one USB Device High Speed Controller, one LCD Controller (for AT91SAM9RL64 only), one AC97 controller, a 2-channel DMA Controller, four USARTs, two SSCs, one SPI, two TWIs, three Timer Counter channels, a 4-channel PWM generator, one Multimedia Card interface and a 6-channel Analog-to-digital converter that also provides resistive touch screen management. The AT91SAM9R64 is architecture on a 6-layer bus matrix. It also features an External Bus Interface capable of interfacing with a wide range of memory and peripheral devices. Some features are not available for AT91SAM9R64 in the 144-ball BGA package.
- Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
- DSP Instruction Extensions
- ARM Jazelle® Technology for Java® Acceleration
- 4 Kbyte Data Cache, 4 Kbyte Instruction Cache, Write Buffer
- 265 MIPS at 240 MHz
- Memory Management Unit
- Embedded ICE™ In-circuit Emulation, Debug Communication Channel Support
- Multi-layer AHB Bus Matrix for Large Bandwidth Transfers
- Six 32-bit-layer Matrix
- Boot Mode Select Option, Remap Command
- One 32-KByte internal ROM, Single-cycle Access at Maximum Speed
- One 64-KByte internal SRAM, Single-cycle Access at Maximum Speed
- 4 Blocks of 16 Kbytes Configurable in TCM or General-purpose SRAM on the AHB Bus Matrix
- Single-cycle Accessible on AHB Bus at Bus Speed
- Single-cycle Accessible on TCM Interface at Processor Speed
- 2-channel DMA
- Memory to Memory Transfer
- 16 Bytes FIFO
- Linked List
- External Bus Interface (EBI)
- EBI Supports SDRAM, Static Memory, ECC-enabled NAND Flash and Compact Flash®
- LCD Controller (for AT91SAM9RL64 only)
- Supports Passive or Active Displays
- Up to 24 Bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode
- Up to 16M Colors in TFT Mode, Resolution Up to 2048×2048, Virtual Screen Support
- High Speed (480 Mbit/s) USB 2.0 Device Controller
- On-Chip High Speed Transceiver, UTMI+ Physical Interface
- Integrated FIFOs and Dedicated DMA
- 4 Kbyte Configurable Integrated DPRAM
- Fully-featured System Controller, including
- Reset Controller, Shutdown Controller
- Four 32-bit Battery Backup Registers for a Total of 16 Bytes
- Clock Generator and Power Management Controller
- Advanced Interrupt Controller and Debug Unit
- Periodic Interval Timer, Watchdog Timer and Real-time Timer and Real-time Clock
- Reset Controller (RSTC)
- Based on Two Power-on Reset Cells
- Reset Source Identification and Reset Output Control
- Shutdown Controller (SHDC)
- Programmable Shutdown Pin Control and Wake-up Circuitry
- Clock Generator (CKGR)
- Selectable 32768 Hz Low-power Oscillator or Internal Low-power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock
- 12 MHz On-chip Oscillator for Main System Clock and USB Clock
- One PLL up to 240 MHz
- One PLL 480 MHz Optimized for USB HS
- Power Management Controller (PMC)
- Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
- Two Programmable External Clock Signals
- Advanced Interrupt Controller (AIC)
