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MCU 16-bit ST10 CISC/RISC ROMLess 3.3V 100-Pin TQFP Tray, ST10R172LT1, STMicroelectronics

ST10R172L architecture combines the advantages of both RISC and CISC processors with an advanced peripheral subsystem. The following block diagram overviews the different on-chip components and the internal bus structure.

  • High Performance 16-bit CPU CPU Frequency: 0 to 50 MHz 40ns instruction cycle time at 50-MHz CPU clock 4-stage pipeline Register-based design with multiple variable register banks Enhanced boolean bit manipulation facilities Additional instructions to support HLL and operating systems Single-cycle context switching support 1024 bytes on-Chip special function register area
  • Memory Organisation 1KByte on-chip RAM Up to 16 MBytes linear address space for code and data (1 MByte with SSP used)
  • External Memory Interface Programmable external bus characteristics for different address ranges 8-bit or 16-bit external data bus Multiplexed or demultiplexed external address/data buses Five programmable chip-select signals Hold and hold-acknowledge bus arbitration support
  • One Channel PWM Unit
  • Fail Safe Protection Programmable watchdog timer Oscillator Watchdog
  • Interrupt 8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller (PEC) 16-priority-level interrupt system with 17 sources, sample-rate down to 40 ns
  • Timers Two multi-functional general purpose timer units with 5 timers Clock Generation via on-chip PLL, or via direct or prescaled clock input
  • Serial Channels Synchronous/asynchronous High-speed-synchronous serial port SSP
  • Up to 77 general purpose I/O lines
  • No bootstrap loader
  • Electrical Characteristics 5V Tolerant I/Os 5V Fail-Safe Inputs (Port 5) Power : 3.3 Volt +/-0.3V Idle and power down modes
  • Support C-compilers, macro-assembler packages, emulators, evaluation boards, HLL-debuggers, simulators, logic analyser disassemblers, programming boards
  • Package 100-Pin Thin Quad Flat Pack (TQFP)

    • Характеристики

    Schedule_b

    8542310000
    Instruction_set_architecture

    CISC, RISC
    Operating_temperature

    0 to 70 °C
    Pin_count

    100
    Product_dimensions

    14 x 14 x 1.4 mm
    Ram_size

    1 KB
    Specifications

    https://4donline.ihs.com/images/VipMasterIC/IC/SGST/SGSTS22617/SGSTS22617-1.pdf?hkey=52A5661711E402568146F3353EA87419
    Supplier_package

    TQFP
    Max_speed

    50 MHz
    Number_of_timers

    5
    Бренд

    Operating_supply_voltage

    3.3 V
    Data_bus_width

    16 Bit
    Country_of_origin

    Malaysia
    Eccn

    3A991.A.2
    Htsn

    8542310001
    Тип интерфейса

    USART
    Number_of_programmable_i_os

    77
    Lead_finish

    Matte Tin
    Max_expanded_memory_size

    16 MB
    Max_power_dissipation

    1000 mW
    Max_processing_temp

    250
    Mounting

    Surface Mount
    Msl_level

    3
    Артикул: ST10R172LT1

    Описание

    ST10R172L architecture combines the advantages of both RISC and CISC processors with an advanced peripheral subsystem. The following block diagram overviews the different on-chip components and the internal bus structure.

  • High Performance 16-bit CPU CPU Frequency: 0 to 50 MHz 40ns instruction cycle time at 50-MHz CPU clock 4-stage pipeline Register-based design with multiple variable register banks Enhanced boolean bit manipulation facilities Additional instructions to support HLL and operating systems Single-cycle context switching support 1024 bytes on-Chip special function register area
  • Memory Organisation 1KByte on-chip RAM Up to 16 MBytes linear address space for code and data (1 MByte with SSP used)
  • External Memory Interface Programmable external bus characteristics for different address ranges 8-bit or 16-bit external data bus Multiplexed or demultiplexed external address/data buses Five programmable chip-select signals Hold and hold-acknowledge bus arbitration support
  • One Channel PWM Unit
  • Fail Safe Protection Programmable watchdog timer Oscillator Watchdog
  • Interrupt 8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller (PEC) 16-priority-level interrupt system with 17 sources, sample-rate down to 40 ns
  • Timers Two multi-functional general purpose timer units with 5 timers Clock Generation via on-chip PLL, or via direct or prescaled clock input
  • Serial Channels Synchronous/asynchronous High-speed-synchronous serial port SSP
  • Up to 77 general purpose I/O lines
  • No bootstrap loader
  • Electrical Characteristics 5V Tolerant I/Os 5V Fail-Safe Inputs (Port 5) Power : 3.3 Volt +/-0.3V Idle and power down modes
  • Support C-compilers, macro-assembler packages, emulators, evaluation boards, HLL-debuggers, simulators, logic analyser disassemblers, programming boards
  • Package 100-Pin Thin Quad Flat Pack (TQFP)

    • Детали

    Schedule_b

    8542310000
    Instruction_set_architecture

    CISC, RISC
    Operating_temperature

    0 to 70 °C
    Pin_count

    100
    Product_dimensions

    14 x 14 x 1.4 mm
    Ram_size

    1 KB
    Specifications

    https://4donline.ihs.com/images/VipMasterIC/IC/SGST/SGSTS22617/SGSTS22617-1.pdf?hkey=52A5661711E402568146F3353EA87419
    Supplier_package

    TQFP
    Max_speed

    50 MHz
    Number_of_timers

    5
    Бренд

    Operating_supply_voltage

    3.3 V
    Data_bus_width

    16 Bit
    Country_of_origin

    Malaysia
    Eccn

    3A991.A.2
    Htsn

    8542310001
    Тип интерфейса

    USART
    Number_of_programmable_i_os

    77
    Lead_finish

    Matte Tin
    Max_expanded_memory_size

    16 MB
    Max_power_dissipation

    1000 mW
    Max_processing_temp

    250
    Mounting

    Surface Mount
    Msl_level

    3

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