Description
True Low Power Platform (as low as 66 µA/MHz, and 0.57 µA for RTC + LVD), 1.6 V to 5.5 V operation, 16 to 512 Kbyte Flash, 41 DMIPS at 32 MHz, for General Purpose Applications.
Ultra-low power consumption technology VDD = single power supply voltage of 1.6 to 5.5 V HALT mode STOP mode SNOOZE mode RL78 CPU core CISC architecture with 3-stage pipeline Minimum instruction execution time: Can be changed from high speed (0.03125 µs: @ 32 MHz operation with high-speed on-chip oscillator) to ultra-low speed (30.5 µs: @ 32.768 kHz operation with subsystem clock) Address space: 1 MB General-purpose registers: (8-bit register × 8) × 4 banks On-chip RAM: 2 to 32 KB Code flash memory Code flash memory: 16 to 512 KB Block size: 1 KB Prohibition of block erase and rewriting (security function) On-chip debug function Self-programming (with boot swap function/flash shield window function)
