MCU 16-bit PIC24 PIC RISC 32KB Flash 2.5V/3.3V 28-Pin SSOP Tube, PIC24FJ32GA102-I/SS, Microchip

The PIC24FJ64GA104 family provides an expanded peripheral feature set and a new option for high-performance applications which may need more than an 8-bit platform, but do not require the power of a digital signal processor. Core Features 16-BIT ARCHITECTURE Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) A 16-element working register array with built-in software stack support A 17 x 17 hardware multiplier with support for integer math Hardware support for 32 by 16-bit division An instruction set that supports multiple addressing modes and is optimized for high-level languages, such as ‘C’ Operational performance up to 16 MIPS POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ64GA104 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, Low-Power Internal RC Oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. Instruction-Based Power-Saving Modes: There are three instruction-based power-saving modes: – Idle Mode – The core is shut down while leaving the peripherals active. – Sleep Mode – The core and peripherals that require the system clock are shut down, leaving the peripherals active that use their own clock or the clock from other devices. – Deep Sleep Mode – The core, peripherals (except RTCC and DSWDT), Flash and SRAM are shut down for optimal current savings to extend battery life for portable applications. OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ64GA104 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: Two Crystal modes using crystals or ceramic resonators. Two External Clock modes offering the option of a divide-by-2 clock output. A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. A Phase Lock Loop (PLL) frequency multiplier available to the external oscillator modes and the FRC Oscillator, which allows clock speeds of up to 32 MHz. A separate Low-Power Internal RC Oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger device.

  • Power Management Modes:
  • Selectable Power Management modes with nanoWatt XLP Technology for Extremely Low Power:
    • Deep Sleep mode allows near total power- down (20 nA typical and 500 nA with RTCC or WDT), along with the ability to wake- up on external triggers, or self- wake on programmable WDT or RTCC alarm
    • Extreme low- power DSBOR for Deep Sleep, LPBOR for all other modes
    • Sleep mode shuts down peripherals and core for substantial power reduction, fast wake- up
    • Idle mode shuts down the CPU and peripherals for significant power reduction, down to 4.5 µA typical
    • Doze mode enables CPU clock to run slower than peripherals
    • Alternate Clock modes allow on- the- fly switching to a lower clock speed for selective power reduction during Run mode, down to 15 µA typical
  • High Performance CPU:
  • Modified Harvard Architecture
  • Up to 16 MIPS Operation @ 32 MHz
  • 8 MHz Internal Oscillator with:
    • 4x PLL option
    • Multiple divide options
  • 17- Bit x 17- Bit Single- Cycle Hardware Fractional/integer Multiplier
  • 32- Bit by 16- Bit Hardware Divider
  • 16 x 16- Bit Working Register Array
  • C Compiler Optimized Instruction Set Architecture:
    • 76 base instructions
    • Flexible addressing modes
  • Linear Program Memory Addressing, up to 12 Mbytes
  • Linear Data Memory Addressing, up to 64 Kbytes
  • Two Address Generation Units for Separate Read and Write Addressing of Data Memory Special Microcontroller Features:
  • Operating Voltage Range of 2.0V to 3.6V
  • Self- reprogrammable under software control
  • 5.5V Tolerant Input (digital pins only)
  • High- Current Sink/Source (18 mA/18 mA) on All I/O pins
  • Flash Program Memory:
    • 10,000 erase/write cycle endurance (minimum)
    • 20- year data retention minimum
    • Selectable write protection boundary
  • Fail- Safe Clock Monitor Operation:
    • Detects clock failure and switches to on- chip FRC Oscillator
  • On- Chip 2.5V Regulator
  • Power- on Reset (POR), Power- up Timer (PWRT) and Oscillator Start- up Timer (OST)
  • Two Flexible Watchdog Timers (WDT) for Reliable Operation:
    • Standard programmable WDT for normal operation
    • Extreme low- power WDT with programmable period of 2 ms to 26 days for Deep Sleep mode
  • In- Circuit Serial Programming™ (ICSP™) and In- Circuit Debug (ICD) via 2 Pins
  • JTAG Boundary Scan Support
  • Analog Features:
  • 10- Bit, up to 13- Channel Analog- to- Digital (A/D) Converter:
    • 500 ksps conversion rate
    • Conversion available during Sleep and Idle
  • Three Analog Comparators with Programmable Input/Output Configuration
  • Charge Time Measurement Unit (CTMU):

Характеристики

Analog_comparators

3

Number_of_timers

5

Operating_supply_voltage

2.5, 3.3 V

Operating_temperature

-40 to 85 °C

Pin_count

28

Product_dimensions

10.2 x 5.3 x 1.75 mm

Screening_level

Industrial

On_chip_adc

10-chx10-bit

Specifications

https://4donline.ihs.com/images/VipMasterIC/IC/MCHP/MCHPS03184/MCHPS03184-1.pdf?hkey=52A5661711E402568146F3353EA87419

Supplier_package

SSOP

Watchdog

2

Max_speed

32 MHz

Schedule_b

8542310000

Instruction_set_architecture

RISC

Бренд

Country_of_origin

Philippines

Data_bus_width

16 Bit

Device_core

PIC

Eccn

3A991.A.2

Htsn

8542310001

Тип интерфейса

I2C/SPI/UART

Number_of_programmable_i_os

21

Lead_finish

Matte Tin

Max_processing_temp

260 °C

Mounting

Surface Mount

Msl_level

1

Артикул: PIC24FJ32GA102-I/SS

Описание

The PIC24FJ64GA104 family provides an expanded peripheral feature set and a new option for high-performance applications which may need more than an 8-bit platform, but do not require the power of a digital signal processor. Core Features 16-BIT ARCHITECTURE Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) A 16-element working register array with built-in software stack support A 17 x 17 hardware multiplier with support for integer math Hardware support for 32 by 16-bit division An instruction set that supports multiple addressing modes and is optimized for high-level languages, such as ‘C’ Operational performance up to 16 MIPS POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ64GA104 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, Low-Power Internal RC Oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. Instruction-Based Power-Saving Modes: There are three instruction-based power-saving modes: – Idle Mode – The core is shut down while leaving the peripherals active. – Sleep Mode – The core and peripherals that require the system clock are shut down, leaving the peripherals active that use their own clock or the clock from other devices. – Deep Sleep Mode – The core, peripherals (except RTCC and DSWDT), Flash and SRAM are shut down for optimal current savings to extend battery life for portable applications. OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ64GA104 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: Two Crystal modes using crystals or ceramic resonators. Two External Clock modes offering the option of a divide-by-2 clock output. A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. A Phase Lock Loop (PLL) frequency multiplier available to the external oscillator modes and the FRC Oscillator, which allows clock speeds of up to 32 MHz. A separate Low-Power Internal RC Oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger device.

  • Power Management Modes:
  • Selectable Power Management modes with nanoWatt XLP Technology for Extremely Low Power:
    • Deep Sleep mode allows near total power- down (20 nA typical and 500 nA with RTCC or WDT), along with the ability to wake- up on external triggers, or self- wake on programmable WDT or RTCC alarm
    • Extreme low- power DSBOR for Deep Sleep, LPBOR for all other modes
    • Sleep mode shuts down peripherals and core for substantial power reduction, fast wake- up
    • Idle mode shuts down the CPU and peripherals for significant power reduction, down to 4.5 µA typical
    • Doze mode enables CPU clock to run slower than peripherals
    • Alternate Clock modes allow on- the- fly switching to a lower clock speed for selective power reduction during Run mode, down to 15 µA typical
  • High Performance CPU:
  • Modified Harvard Architecture
  • Up to 16 MIPS Operation @ 32 MHz
  • 8 MHz Internal Oscillator with:
    • 4x PLL option
    • Multiple divide options
  • 17- Bit x 17- Bit Single- Cycle Hardware Fractional/integer Multiplier
  • 32- Bit by 16- Bit Hardware Divider
  • 16 x 16- Bit Working Register Array
  • C Compiler Optimized Instruction Set Architecture:
    • 76 base instructions
    • Flexible addressing modes
  • Linear Program Memory Addressing, up to 12 Mbytes
  • Linear Data Memory Addressing, up to 64 Kbytes
  • Two Address Generation Units for Separate Read and Write Addressing of Data Memory Special Microcontroller Features:
  • Operating Voltage Range of 2.0V to 3.6V
  • Self- reprogrammable under software control
  • 5.5V Tolerant Input (digital pins only)
  • High- Current Sink/Source (18 mA/18 mA) on All I/O pins
  • Flash Program Memory:
    • 10,000 erase/write cycle endurance (minimum)
    • 20- year data retention minimum
    • Selectable write protection boundary
  • Fail- Safe Clock Monitor Operation:
    • Detects clock failure and switches to on- chip FRC Oscillator
  • On- Chip 2.5V Regulator
  • Power- on Reset (POR), Power- up Timer (PWRT) and Oscillator Start- up Timer (OST)
  • Two Flexible Watchdog Timers (WDT) for Reliable Operation:
    • Standard programmable WDT for normal operation
    • Extreme low- power WDT with programmable period of 2 ms to 26 days for Deep Sleep mode
  • In- Circuit Serial Programming™ (ICSP™) and In- Circuit Debug (ICD) via 2 Pins
  • JTAG Boundary Scan Support
  • Analog Features:
  • 10- Bit, up to 13- Channel Analog- to- Digital (A/D) Converter:
    • 500 ksps conversion rate
    • Conversion available during Sleep and Idle
  • Three Analog Comparators with Programmable Input/Output Configuration
  • Charge Time Measurement Unit (CTMU):

Детали

Analog_comparators

3

Number_of_timers

5

Operating_supply_voltage

2.5, 3.3 V

Operating_temperature

-40 to 85 °C

Pin_count

28

Product_dimensions

10.2 x 5.3 x 1.75 mm

Screening_level

Industrial

On_chip_adc

10-chx10-bit

Specifications

https://4donline.ihs.com/images/VipMasterIC/IC/MCHP/MCHPS03184/MCHPS03184-1.pdf?hkey=52A5661711E402568146F3353EA87419

Supplier_package

SSOP

Watchdog

2

Max_speed

32 MHz

Schedule_b

8542310000

Instruction_set_architecture

RISC

Бренд

Country_of_origin

Philippines

Data_bus_width

16 Bit

Device_core

PIC

Eccn

3A991.A.2

Htsn

8542310001

Тип интерфейса

I2C/SPI/UART

Number_of_programmable_i_os

21

Lead_finish

Matte Tin

Max_processing_temp

260 °C

Mounting

Surface Mount

Msl_level

1