Описание
The PIC24FJ256GB210 family enhances on the existing line of Microchip‘s 16-bit microcontrollers, adding a large data RAM, up to 96 Kbytes. The PIC24FJ256GB210 family allows the CPU to fetch data directly from an external memory device using the EPMP module. Core Features 16-BIT ARCHITECTURE Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC Digital Signal Controllers (DSCs). The PIC24F CPU core offers a wide range of enhancements, such as: 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces Linear addressing of up to 12 Mbytes (program space) and 32 Kbytes (data) A 16-element working register array with built-in software stack support A 17 x 17 hardware multiplier with support for integer math Hardware support for 32 by 16-bit division An instruction set that supports multiple addressing modes and is optimized for high-level languages, such as ‘C’ Operational performance up to 16 MIPS POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ256GB210 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active with a single instruction in software. OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ256GB210 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: Two Crystal modes using crystals or ceramic resonators. Two External Clock modes offering the option of a divide-by-2 clock output. A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz. A separate Low-Power Internal RC Oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor (FSCM). This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger, or even in jumping from 64-pin to 100-pin devices. The PIC24F family is pin compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device.
- USB v2.0 On- The- Go (OTG) Compliant
- Dual Role Capable – Can act as either Host or Peripheral
- Low- Speed (1.5 Mbps) and Full- Speed (12 Mbps) USB Operation in Host mode
- Full Speed USB Operation in Device mode
- High Precision PLL for USB
- Supports up to 32 Endpoints (16 bidirectional):
- USB module can use the internal RAM location from 0x800 to 0xFFFF as USB endpoint buffers
- On Chip USB Transceiver with Interface for Off- Chip Transceiver
- Supports Control, Interrupt, Isochronous and Bulk Transfers
- On- Chip Pull- up and Pull- Down Resistors
- Peripheral Features:
- Enhanced Parallel Master Port/Parallel Slave Port (EPMP/PSP):
- Direct access from CPU with an Extended Data Space (EDS) interface
- 4, 8 and 16- bit wide data bus
- Up to 23 programmable address lines
- Up to 2 chip select lines
- Up to 2 Acknowledgement lines (one per chip select)
- Programmable address/data multiplexing
- Programmable address and data Wait states
- Programmable polarity on control signals
- Peripheral Pin Select:
- Up to 44 available pins (100- pin devices)
- Three 3- Wire/4- Wire SPI modules (supports 4 Frame modes)
- Three I2C modules Supporting Multi- Master/Slave modes and 7- Bit/10- Bit Addressing
- Four UART modules:
- Supports RS- 485, RS- 232, LIN/J2602 protocols and IrDA®
- Five 16- Bit Timers/Counters with Programmable Prescaler
- Nine 16- Bit Capture Inputs, each with a Dedicated Time Base
- Nine 16- Bit Compare/PWM Outputs, each with a Dedicated Time Base
- Hardware Real- Time Clock and Calendar (RTCC)
- Enhanced Programmable Cyclic Redundancy Check (CRC) Generator
- Up to 5 External Interrupt Sources High- Performance CPU
- Modified Harvard Architecture
- Up to 16 MIPS Operation at 32 MHz
- 8 MHz Internal Oscillator
- 17- Bit x 17- Bit Single- Cycle Hardware Multiplier
- 32- Bit by 16- Bit Hardware Divider
- 16 x 16- Bit Working Register Array
- C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes
- Linear Program Memory Addressing, up to 12 Mbytes
- Data Memory Addressing, up to 16 Mbytes:
- 2K SFR space
- 30K linear data memory
- 66K extended data memory
- Remaining (from 16 Mbytes) memory (external) can be accessed using extended data Memory (EDS) and EPMP (EDS is divided into 32- Kbyte pages)
- Two Address Generation Units for Separate Read and Write Addressing of Data Memory Power Management:
- On- Chip Voltage Regulator of 1.8V
- Run Mode: 800 µA/MIPS, 3.3V Typical
- Sleep mode Current Down to 20 µA, 3.3V Typical
- Standby Current with 32 kHz Oscillator: 22 µA, 3.3V Typical
- Analog Features:
- 10- Bit, up to 24- Channel Analog- to- Digital (A/D) Converter at 500 ksps:
- Operation is possible in Sleep mode
- Band gap reference input feature
- Three Analog Comparators with Programmable Input/Output Configuration
- Charge Time Measurement Unit (CTMU):
- Supports capacitive touch sensing for touch screens and capacitive switches
- Minimum time measurement setting at 100 ps
- Available LVD Interrupt VLVD Level
- Special Microcontroller Features:
- Operating Voltage Range of 2.2V to 3.6V
- 5.5V Tolerant Input (digital pins only)
- Configurable Open- Drain Outputs on Digital I/O Ports
- High- Current Sink/Source (18 mA/18 mA) on all I/O Ports
- Selectable Power Management modes:
- Sleep, Idle and Doze modes with fast wake- up
