MCU 16-bit MCS96 CISC ROMLess 5V 100-Pin PQFP, S80C196NP25, Intel

The 16-bit 8XC196NP CHMOS microcontrollers are designed to handle highspeed calculations and fast input/output (I/O) operations. They share a common architecture and instruction set with other members of the MCS 96 microcontroller family. In addition to their 16-bit address/data buses, both microcontrollers have extended addressing ports consisting of 4 external address pins, for a total of 20 address pins. With 20 address pins, these microcontrollers can access up to 1 Mbyte of linear address space. Both devices also have chip-select units that provide a glueless interface to external memory devices. The extended addressing port and chipselect unit enable these microcontrollers to handle larger, more complex programs and to access more external memory at a faster rate than could earlier MCS 96 microcontrollers. The 8XC196NP is a pin-compatible and have identical cores. However, the 80C196NU can operate at twice the frequency of the 8XC196NP also employs an accumulator and enhanced multiplication instructions to support multiply-accumulate operations. The 80C196NU is the first MCS 96 microcontroller with this capability. This chapter provides a high-level overview of the architecture.

  • 25 MHz Operation at 4.5–5.5 Volts
  • 1 Mbyte of Linear Address Space
  • Optional 4 Kbytes of ROM
  • 1000 Bytes of Register RAM
  • Register-register Architecture
  • 32 I/O Port Pins
  • 16 Prioritized Interrupt Sources
  • 4 External Interrupt Pins and NMI Pin
  • 2 Flexible 16-bit Timer/Counters with Quadrature Counting Capability
  • 3 Pulse-width Modulator (PWM) Outputs with High Drive Capability
  • Full-duplex Serial Port with Dedicated Baud-rate Generator
  • Peripheral Transaction Server
  • Event Processor Array (EPA) with 4 High-speed Capture/Compare Channels
  • Chip-select Unit
    • 6 Chip Select Pins
    • Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select
    • Programmable Wait States (0, 1, 2, or 3) for Each Chip Select
    • Programmable Bus Width (8- or 16- bit) for Each Chip Select
    • Programmable Address Range for Each Chip Select
  • 1.12 µs 16 × 16 Unsigned Multiplication
  • 1.92 µs 32/16 Unsigned Division
  • 100-pin SQFP or 100-pin QFP Package
  • Complete System Development Support
  • High-speed CHMOS Technology

Характеристики

Schedule_b

8542310000

Instruction_set_architecture

CISC

Operating_temperature

0 to 70 °C

Pin_count

100

Product_dimensions

19.13 x 19.13 x 3.55 mm

Ram_size

1000 byte

Screening_level

Commercial

Supplier_package

PQFP

Max_speed

25 MHz

Number_of_timers

2

Бренд

Operating_supply_voltage

5 V

Data_bus_width

16 Bit

Country_of_origin

United States

Eccn

EAR99

Htsn

8542310001

Number_of_programmable_i_os

32

Lead_finish

Tin/Lead

Max_expanded_memory_size

1 MB

Max_operating_supply_voltage

5.5 V

Max_power_dissipation

1500 mW

Max_processing_temp

225

Min_operating_supply_voltage

4.5 V

Mounting

Surface Mount

Артикул: S80C196NP25

Описание

The 16-bit 8XC196NP CHMOS microcontrollers are designed to handle highspeed calculations and fast input/output (I/O) operations. They share a common architecture and instruction set with other members of the MCS 96 microcontroller family. In addition to their 16-bit address/data buses, both microcontrollers have extended addressing ports consisting of 4 external address pins, for a total of 20 address pins. With 20 address pins, these microcontrollers can access up to 1 Mbyte of linear address space. Both devices also have chip-select units that provide a glueless interface to external memory devices. The extended addressing port and chipselect unit enable these microcontrollers to handle larger, more complex programs and to access more external memory at a faster rate than could earlier MCS 96 microcontrollers. The 8XC196NP is a pin-compatible and have identical cores. However, the 80C196NU can operate at twice the frequency of the 8XC196NP also employs an accumulator and enhanced multiplication instructions to support multiply-accumulate operations. The 80C196NU is the first MCS 96 microcontroller with this capability. This chapter provides a high-level overview of the architecture.

  • 25 MHz Operation at 4.5–5.5 Volts
  • 1 Mbyte of Linear Address Space
  • Optional 4 Kbytes of ROM
  • 1000 Bytes of Register RAM
  • Register-register Architecture
  • 32 I/O Port Pins
  • 16 Prioritized Interrupt Sources
  • 4 External Interrupt Pins and NMI Pin
  • 2 Flexible 16-bit Timer/Counters with Quadrature Counting Capability
  • 3 Pulse-width Modulator (PWM) Outputs with High Drive Capability
  • Full-duplex Serial Port with Dedicated Baud-rate Generator
  • Peripheral Transaction Server
  • Event Processor Array (EPA) with 4 High-speed Capture/Compare Channels
  • Chip-select Unit
    • 6 Chip Select Pins
    • Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select
    • Programmable Wait States (0, 1, 2, or 3) for Each Chip Select
    • Programmable Bus Width (8- or 16- bit) for Each Chip Select
    • Programmable Address Range for Each Chip Select
  • 1.12 µs 16 × 16 Unsigned Multiplication
  • 1.92 µs 32/16 Unsigned Division
  • 100-pin SQFP or 100-pin QFP Package
  • Complete System Development Support
  • High-speed CHMOS Technology

Детали

Schedule_b

8542310000

Instruction_set_architecture

CISC

Operating_temperature

0 to 70 °C

Pin_count

100

Product_dimensions

19.13 x 19.13 x 3.55 mm

Ram_size

1000 byte

Screening_level

Commercial

Supplier_package

PQFP

Max_speed

25 MHz

Number_of_timers

2

Бренд

Operating_supply_voltage

5 V

Data_bus_width

16 Bit

Country_of_origin

United States

Eccn

EAR99

Htsn

8542310001

Number_of_programmable_i_os

32

Lead_finish

Tin/Lead

Max_expanded_memory_size

1 MB

Max_operating_supply_voltage

5.5 V

Max_power_dissipation

1500 mW

Max_processing_temp

225

Min_operating_supply_voltage

4.5 V

Mounting

Surface Mount