Description
The H8/3052BF is a group of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas Technology architecture.The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU, enabling easy porting of software from the H8/300 Series.The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller (DMAC), a refresh controller, and other facilities.The H8/3052BF has 512 kbytes of ROM and 8 kbytes of RAM.Seven MCU operating modes offer a choice of data bus width and address space size. The modes (modes 1 to 7) include one single-chip mode and six expanded modes.The H8/3052BF has an F-ZTAT version with on-chip flash memory that can be programmed on-board.
- Upward-compatible with the H8/300 CPU at the object-code level
- General-register machine
- Sixteen 16-bit general registers (also usable as + eight 16-bit registers or eight 32-bit registers)
- High-speed operation
- Maximum clock rate: 25 MHz
- Add/subtract: 80 ns
- Multiply/divide: 560 ns
- 16-Mbyte address space
- Instruction features
- 8/16/32-bit data transfer, arithmetic, and logic instructions
- Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16bits)
- Signed and unsigned divide instructions (16 bits ˜ 8 bits, 32 bits ˜ 16bits)
- Bit accumulator function
- Bit manipulation instructions with register-indirect specification of bit positions
- Flash memory: 512 kbytes
- RAM: 8 kbytes
