Description
The Am186CH HDLC microcontroller is a member of AMD’s Comm86 family of communications-specific microcontrollers. The microcontroller is a derivative of the Am186CC communications controller and is pincompatible with that device. The Am186CH HDLC microcontroller is a costeffective, high-performance microcontroller solution for communications applications. This highly integrated microcontroller enables customers to save system costs and increase performance over 8-bit microcontrollers and other 16-bit microcontrollers. The microcontroller offers the advantages of the x86 development environment’s widely available native development tools, applications, and system software. Additionally, the microcontroller uses the industrystandard 186 instruction set that is part of the AMD E86 family, which continually offers instruction-setcompatible upgrades. Built into the Am186CH HDLC microcontroller is a wide range of communications features required in many communications applications, including High-level Data Link Control (HDLC). Comprehensive development support is available from AMD and its FusionE86SM partners. A customer development platform board is available. AMD and its FusionE86 partners also offer boards, schematics, drivers, protocol stacks, and routing software to enable fast time to market.
- E86™ family of x86 embedded processors offers improved time-to-market
- Software migration (backwards- and upwardscompatible)
- World-class development tools, applications, and system software
- Serial Communications Peripherals
- Two High-level Data Link Control (HDLC) channels
- Two independent Time Slot Assigners (TSAs)
- Physical interface for HDLC channels can be raw DCE or PCM Highway
- High-Speed UART with autobaud
- UART
- Synchronous serial interface (SSI)
- SmartDMA™ channels (4) to support HDLC
- System Peripherals
- Three programmable 16-bit timers
- Hardware watchdog timer
- General-purpose DMA (4 channels)
- Programmable I/O (48 PIO signals)
- Interrupt Controller (36 maskable interrupts)
- Memory and Peripheral Interface
- Integrated DRAM controller
- Glueless interface to RAM/ROM/Flash memory (55-ns Flash memory required for zero-wait-state operation at 50 MHz)
- Fourteen chip selects (8 peripherals, 6 memory)
- External bus mastering support
- Multiplexed and nonmultiplexed address/data bus
- Programmable bus sizing
- 8-bit boot option
- Available in the following package:
- 160-pin plastic quad flat pack (PQFP)
- 25-, 40-, and 50-MHz operating frequencies
- Low-voltage operation, VCC = 3.3 V ± 0.3 V
- Commercial and industrial temperature rating
- 5-V-tolerant I/O (3.3-V output levels)
