Description
The family of 16-bit CompactRISC microcontroller is based on a Reduced Instruction Set Computer (RISC) architecture. The device operates as a complete microcomputer with all system timing, interrupt logic, flash program memory or ROM memory, RAM, EEPROM data memory, and I/O ports included on-chip. It is ideally suited to a wide range of embedded controller applications because of its high performance, on-chip integrated features and low power consumption resulting in decreased system cost.The device offers the high performance of a RISC architecture while retaining the advantages of a traditional Complex Instruction Set Computer (CISC): compact code, onchip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million instructions per second (MIPS) at a clock rate of 24 MHz.
- CPU Features
- Fully static core, capable of operating at any rate from 0 to 24 MHz (4 MHz minimum in active mode)
- 50 ns instruction cycle time with a 20 MHz external clock frequency
- Multi-source vectored interrupts (internal, external, and on-chip peripheral)
- Dual clock and reset
- On-chip power-on reset
- On-Chip Memory
- Up to 64K bytes flash EEPROM program memory; can be programmed, erased, and reprogrammed by software (100K cycles)
- 3K bytes of static RAM data memory
- For flash program memory devices, 1.5k bytes flash EEPROM memory is available to store boot loader code (100K cycles)
- 2K bytes of non-volatile EEPROM data memory with low endurance (25K cycles) and 128 bytes with high endurance (100K cycles)
- On-Chip Peripherals
- Two Universal Synchronous/Asynchronous Receiver/ Transmitter (USART) devices
- Programmable Idle Timer and real-time clock (T0)
- Two dual 16-bit multi-function timers (MFT1 and MFT2)
- 8/16-bit SPI/MICROWIRE-PLUS serial interface
- 12-channel, 8-bit Analog-to-Digital (A/D) converter with external voltage reference, programmable sample-and-hold delay, and programmable conversion frequency
- ACCESS.bus synchronous serial bus
