MCU 16-bit C166 CISC/RISC ROMLess 5V, C161CSLFCAFXUMA1, Infineon

MCU 16-bit C166 CISC/RISC ROMLess 5V

  • High Performance 16-bit CPU with 4-Stage Pipeline
    • 80 ns Instruction Cycle Time at 25 MHz CPU Clock
    • 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
    • Enhanced Boolean Bit Manipulation Facilities
    • Additional Instructions to Support HLL and Operating Systems
    • Register-Based Design with Multiple Variable Register Banks
    • Single-Cycle Context Switching Support
    • 16 MBytes Total Linear Address Space for Code and Data
    • 1024 Bytes On-Chip Special Function Register Area
  • 16-Priority-Level Interrupt System with 59 Sources, Sample-Rate down to 40 ns
  • 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)
  • Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input
    • Additional 32 kHz Oscillator
  • On-Chip Memory Modules
    • 2 KBytes On-Chip Internal RAM (IRAM)
    • 8 KBytes On-Chip Extension RAM (XRAM)
    • 256 KBytes On-Chip Mask ROM
  • On-Chip Peripheral Modules
    • 12-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 µs
    • Two 16-Channel Capture/Compare Units (eight IO lines each)
    • Two Multi-Functional General Purpose Timer Units with 5 Timers
    • Two Asynchronous/Synchronous Serial Channels
    • High-Speed Synchronous Serial Channel (SPI)
    • On-Chip CAN Interface (Rev. 2.0B active, Full CAN / Basic CAN) with 15 Message Objects
    • IIC Bus Interface (10-bit Addressing, 400 kHz) with 2 Channels (multiplexed)
    • On-Chip Real Time Clock
  • Up to 16 MBytes External Address Space for Code and Data
    • Programmable External Bus Characteristics for Different Address Ranges
    • Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width
    • Five Programmable Chip-Select Signals
    • Hold- and Hold-Acknowledge Bus Arbitration Support
  • Idle, Sleep, and Power Down Modes with Flexible Power Management
  • Programmable Watchdog Timer and Oscillator Watchdog
  • Up to 93 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
  • Supported by a Large Range of Development Tools like C-Compilers,Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
  • On-Chip Bootstrap Loader
  • 128-Pin TQFP Package

Характеристики

Schedule_b

8542310000

Number_of_timers

5

Operating_temperature

-40 to 85 °C

Product_dimensions

mm

Program_memory_type

ROMLess

Ram_size

10 KB

On_chip_adc

12-chx10-bit

Specifications

http://www.infineon.com/dgdl/c167cs4r_ds_v2.2_2001_08.pdf?folderId=db3a304412b407950112b41e5aa03294&fileId=db3a304412b407950112b41e5afd3295&sId=db3a30433a047ba0013a07218bd70210

Watchdog

1

Max_speed

25 MHz

Operating_supply_voltage

5 V

Instruction_set_architecture

CISC, RISC

Бренд

Data_bus_width

16 Bit

Eccn

EAR99

Htsn

8542310001

Тип интерфейса

SDLM

Number_of_programmable_i_os

93

Max_expanded_memory_size

16 MB

Max_operating_supply_voltage

5.5 V

Max_power_dissipation

1500 mW

Min_operating_supply_voltage

4.5 V

Артикул: C161CSLFCAFXUMA1

Описание

MCU 16-bit C166 CISC/RISC ROMLess 5V

  • High Performance 16-bit CPU with 4-Stage Pipeline
    • 80 ns Instruction Cycle Time at 25 MHz CPU Clock
    • 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
    • Enhanced Boolean Bit Manipulation Facilities
    • Additional Instructions to Support HLL and Operating Systems
    • Register-Based Design with Multiple Variable Register Banks
    • Single-Cycle Context Switching Support
    • 16 MBytes Total Linear Address Space for Code and Data
    • 1024 Bytes On-Chip Special Function Register Area
  • 16-Priority-Level Interrupt System with 59 Sources, Sample-Rate down to 40 ns
  • 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)
  • Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input
    • Additional 32 kHz Oscillator
  • On-Chip Memory Modules
    • 2 KBytes On-Chip Internal RAM (IRAM)
    • 8 KBytes On-Chip Extension RAM (XRAM)
    • 256 KBytes On-Chip Mask ROM
  • On-Chip Peripheral Modules
    • 12-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 µs
    • Two 16-Channel Capture/Compare Units (eight IO lines each)
    • Two Multi-Functional General Purpose Timer Units with 5 Timers
    • Two Asynchronous/Synchronous Serial Channels
    • High-Speed Synchronous Serial Channel (SPI)
    • On-Chip CAN Interface (Rev. 2.0B active, Full CAN / Basic CAN) with 15 Message Objects
    • IIC Bus Interface (10-bit Addressing, 400 kHz) with 2 Channels (multiplexed)
    • On-Chip Real Time Clock
  • Up to 16 MBytes External Address Space for Code and Data
    • Programmable External Bus Characteristics for Different Address Ranges
    • Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width
    • Five Programmable Chip-Select Signals
    • Hold- and Hold-Acknowledge Bus Arbitration Support
  • Idle, Sleep, and Power Down Modes with Flexible Power Management
  • Programmable Watchdog Timer and Oscillator Watchdog
  • Up to 93 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
  • Supported by a Large Range of Development Tools like C-Compilers,Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
  • On-Chip Bootstrap Loader
  • 128-Pin TQFP Package

Детали

Schedule_b

8542310000

Number_of_timers

5

Operating_temperature

-40 to 85 °C

Product_dimensions

mm

Program_memory_type

ROMLess

Ram_size

10 KB

On_chip_adc

12-chx10-bit

Specifications

http://www.infineon.com/dgdl/c167cs4r_ds_v2.2_2001_08.pdf?folderId=db3a304412b407950112b41e5aa03294&fileId=db3a304412b407950112b41e5afd3295&sId=db3a30433a047ba0013a07218bd70210

Watchdog

1

Max_speed

25 MHz

Operating_supply_voltage

5 V

Instruction_set_architecture

CISC, RISC

Бренд

Data_bus_width

16 Bit

Eccn

EAR99

Htsn

8542310001

Тип интерфейса

SDLM

Number_of_programmable_i_os

93

Max_expanded_memory_size

16 MB

Max_operating_supply_voltage

5.5 V

Max_power_dissipation

1500 mW

Min_operating_supply_voltage

4.5 V