Description
The TMS570LS3137 device is a high-performance automotive-grade microcontroller family for safetysystems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC onboth the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheralI/Os. The TMS570LS3137 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers anefficient 1.66 DMIPS/MHz, and has configurations that can run up to 180 MHz, providing up to 298DMIPS. The device supports the word-invariant big-endian [BE32] format. The TMS570LS3137 device has 3MB of integrated flash and 256KB of data RAM. Both the flash and RAMhave single-bit error correction and double-bit error detection. The flash memory on this device is anonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data businterface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, anderase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-wordmodes. The TMS570LS3137 device features peripherals for real-time control-based applications, including twoNext Generation High-End Timer (N2HET) timing coprocessors and two 12-bit Analog-to-DigitalConverters (ADCs) supporting up to 24 inputs. The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-timeapplications. The timer is software-controlled, using a reduced instruction set, with a specialized timermicromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs,capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiringmultiple sensor information and drive actuators with complex and accurate time pulses. A High-End TimerTransfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory.A Memory Protection Unit (MPU) is built into the HTU. The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected bufferRAM each. The MibADC channels can be converted individually or can be grouped by software forsequential conversion sequences. Sixteen channels are shared between the two MibADCs. There arethree separate groupings. Each sequence can be converted once when triggered or configured forcontinuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with olderdevices or faster conversion time is desired.
- High-Performance Automotive-Grade
- Multiple Communication Interfaces Microcontroller for Safety-Critical Applications
- 10/100 Mbps Ethernet MAC (EMAC)
- Dual CPUs Running in Lockstep
- IEEE 802.3 Compliant (3.3-V I/O Only)
- ECC on Flash and RAM Interfaces
- Supports MII, RMII, and MDIO
- Built-In Self-Test (BIST) for CPU and On-chip
- FlexRay Controller With Two Channels RAMs
- 8KB of Message RAM With Parity Protection
- Error Signaling Module With Error Pin
- Dedicated Transfer Unit (FTU)
- Voltage and Clock Monitoring
- Three CAN Controllers (DCANs)
- ARM® Cortex®
- R4F 32-Bit RISC CPU
- 64 Mailboxes, Each With Parity Protection
- Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline
- Compliant to CAN Protocol Version 2.0B
- FPU With Single- and Double-Precision
- Standard Serial Communication Interface (SCI)
- 12-Region Memory Protection Unit (MPU)
- Local Interconnect Network (LIN) Interface
- Open Architecture With Third-Party Support Controller
- Operating Conditions
- Compliant to LIN Protocol Version 2.1
- System Clock up to 180 MHz
- Can be Configured as a Second SCI
- Core Supply Voltage (VCC): 1.2 V Nominal
- Inter-Integrated Circuit (I2C)
- I/O Supply Voltage (VCCIO): 3.3 V Nominal
- Three Multibuffered Serial Peripheral Interfaces
- ADC Supply Voltage (VCCAD): 3.0 to 5.25 V (MibSPIs)
- Integrated Memory
- 128 Words With Parity Protection Each
- 3MB of Program Flash With ECC
- Two Standard Serial Peripheral Interfaces
- 256KB of RAM With ECC (SPIs)
- 64KB of Flash With ECC for Emulated
- Two Next Generation High-End Timer (N2HET) EEPROM Modules
- 16-Bit External Memory Interface
- N2HET1: 32 Programmable Channels
- Common Platform Architecture
- N2HET2: 18 Programmable Channels
- Consistent Memory Map Across Family
- 160-Word Instruction RAM Each With Parity
- Real-Time Interrupt (RTI) Timer OS Timer Protection
- 96-Channel Vectored Interrupt Module (VIM)Each
- N2HET Includes Hardware Angle Generator
- 2-Channel Cyclic Redundancy Checker (CRC)
- Dedicated High-End Transfer Unit (HTU)
- Direct Memory Access (DMA) Controller MPU for Each N2HET
- 16 Channels and 32 Control Packets
- Two 12-Bit Multibuffered ADC Modules
- Parity Protection for Control Packet RAM
- ADC1: 24 Channels
- DMA Accesses Protected by Dedicated MPU
- ADC2: 16 Channels Shared With ADC1
- Frequency-Modulated Phase-Locked Loop
- 64 Result Buffers With Parity Protection Each (FMPLL) With Built-In Slip Detector
- General-Purpose Input/Output (GPIO) Pins
- Separate Nonmodulating PLL for FlexRay™ Capable of Generating Interrupts
- Trace and Calibration Capabilities
- Sixteen Pins on the ZWT Package
- Embedded Trace Macrocell (ETM-R4)
- Four Pins on the PGE Package
- Data Modification Module (DMM)
- IEEE 1149.1 JTAG, Boundary Scan and ARM
- RAM Trace Port (RTP) CoreSight™ Components
- Parameter Overlay Module (POM)
- JTAG Security Module
- Packages
- 144-Pin Quad Flatpack (PGE) [Green]
- 337-Ball Grid Array (ZWT) [Green]
