MCU 16-bit/32-bit RM48Lx50 ARM Cortex R4F RISC 2048KB Flash 1.2V/3.3V 144-Pin LQFP Tray, RM48L550PGET, Texas Instruments

Description

The RM48Lx50device is ahigh-performance microcontroller family forsafety systems. The safety architecture includesdual CPUs in lockstep, CPUand memory BIST logic, ECC on both the flash and the data SRAM, parityonperipheral memories, and loopback capability on peripheral I/Os. The RM48Lx50deviceintegrates the ARM Cortex-R4FFloating-Point CPU. The CPU offers an efficient 1.66 DMIPS/MHz, and hasconfigurations thatcan run up to 200MHz, providing up to 332 DMIPS.The device supports thelittle-endian [LE]format. The RM48L950 device has 3MB of integrated flash and 256KB of data RAM. The RM48L750 device has 2MB of integrated flash and 256KB of data RAM. The RM48L550device has 2MB ofintegrated flash and 192KB of data RAM.Both the flash and RAM have single-bit error correction and double-bit error detection. Theflash memory on thisdevice is a nonvolatile, electrically erasable, andprogrammable memory implemented with a64-bit-wide data bus interface. Theflash operates on a 3.3-V supply input (same level as I/Osupply) for allread, program, and erase operations. When in pipeline mode, the flash operateswitha system clock frequency of up to 200 MHz.The SRAM supportssingle-cycle read and write accesses in byte, halfword, word, and double-word modes. The RM48Lx50devicefeatures peripherals for real-time control-basedapplications, including twoNext Generation High-End Timer (N2HET) timingcoprocessors and two 12-bit Analog-to-DigitalConverters (ADCs) supporting upto 24 inputs. The N2HET is an advanced intelligent timer that provides sophisticated timingfunctionsfor real-time applications. The timer is software-controlled, usinga reduced instruction set, witha specialized timer micromachine and anattached I/O port. The N2HET can be used forpulse-width-modulated outputs,capture or compare inputs, or GPIO. The N2HET is especially wellsuited forapplications requiring multiple sensor information and drive actuators withcomplex andaccurate time pulses. A High-End Timer Transfer Unit (HTU) canperform DMA-type transactions totransfer N2HET data to or from main memory.A Memory Protection Unit (MPU) is built into theHTU. Thedevice has two 12-bit-resolution MibADCs with 24 channels and 64 wordsof parity-protected bufferRAM each. The MibADC channels can be convertedindividually or can be grouped by software forsequential conversionsequences. Sixteen channels are shared between the two MibADCs. There are three separate groupings. Each sequence can be converted once when triggered orconfigured forcontinuous conversion mode. The MibADC has a 10-bit mode foruse when compatibility with olderdevices or faster conversion time isdesired.