Описание
The LPC2114 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 128/256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. With their compact 64-pin package, low power consumption, various 32-bit timers, 4-channel 10-bit ADC, PWM channels and 46 fast GPIO lines with up to nine external interrupt pins these microcontrollers are particularly suitable for industrial control, medical systems, access control and point-of-sale. With a wide range of serial communications interfaces, they are also very well suited for communication gateways, protocol converters and embedded soft modems as well as many other general-purpose applications.
- 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
- 16 kB on-chip static RAM.
- CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 0.15 V).
- Embedded Trace Macrocell (ETM) enables non-intrusive high speed real-time tracing of instruction execution.
- Four-channel 10-bit ADC with conversion time as low as 2.44 µs
- Two 32-bit timers (with four capture and four compare channels), PWM unit (six outputs), Real-Time Clock (RTC) and watchdog.
- Multiple serial interfaces including two UARTs (16C550), Fast I2C-bus (400 kbit/s) and two SPIs.
- 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked Loop with settling time of 100 µs
- Vectored Interrupt Controller with configurable priorities and vector addresses.
- Up to forty-six 5 V tolerant general purpose I/O pins. Up to nine edge or level sensitive external interrupt pins available.
- On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
- Two low power modes, Idle and Power-down.
- Processor wake-up from Power-down mode via external interrupt.
- Individual enable/disable of peripheral functions for power optimization.
