Description
The H8/3006 and H8/3007 are a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas architecture.The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed.It can address a 16-Mbyte linear address space.Its instruction set is upward-compatible at the object-code level with the H8/300 CPU, enabling easy porting of software from the H8/300 Series.The on-chip system supporting functions include RAM, a 16-bit timer, an 8-bit timer, a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller (DMAC), and other facilities.
- Upward-compatible with the H8/300 CPU at the object-code level General-register machine
- Sixteen 16-bit general registers (also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight 32-bit registers)
- High-speed operation
- Maximum clock rate: 20 MHz
- Add/subtract: 100 ns
- Multiply/divide: 700 ns
- 16-Mbyte address space
- Instruction features
- 8/16/32-bit data transfer, arithmetic, and logic instructions
- Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)
- Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
- Bit accumulator function
- Bit manipulation instructions with register-indirect specification of bit positions
