Mapper T1/E1/J1SONET/SDH 10Mbps/100Mbps 1.8V/3.3V 400-Pin BGA

The DS33R41 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over four interleaved T1/E1/J1 lines using a robust, balanced, and programmable inverse multiplexing. Four integrated T1/E1/J1 transceivers provide framing and line interfacing functionality. The device performs store-and-forward of packets with full wire-speed transport capability. The built-in committed information rate (CIR) controller provides fractional bandwidth allocation up to the line rate in increments of 512kbps.

• 10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control
• Layer 1 Inverse Multiplexing Over Four T1/E1/J1 Lines Through the Integrated Framers and LIUs
• Supports Up to 7.75ms Differential Delay
• Aggregate Bandwidth from Up to Four T1/E1/J1 Links
• T1/E1 Signaling Capability for OAM
• HDLC/LAPS Encapsulation with Programmable FCS, Interframe Fill
• CIR Controller Provides Fractional Allocations in 512kbps Increments
• Programmable BERTs
• External 16MB, 100MHz SDRAM Buffering
• Parallel Microprocessor Interface
• 1.8V, 3.3V Power Supplies
• IEEE 1149.1 JTAG Support