ISDN S/T/U HDLC Interface 1-Line 192Kbps 3.3V 64-Pin MQFP

The ISDN PC Adapter Circuit Extended IPAC-X integrates all necessary functions for a host based ISDN access solution on a single chip. It is based on the IPAC PSB 2115, combining the functions of ISAC-S PEB 2086 and HSCX-TE PSB 21525, with enhanced features and functionality.It includes the S-transceiver (Layer 1), an HDLC controller for the D-channel and two protocol controllers for each B-channel. They can be used for HDLC protocol or transparent access.The system integration is simplified by several configurations of the parallel microcontroller interface selected via pin strapping. They include multiplexed and demultiplexed interface selection as well as the optional indirect register access mechanism which reduces the number of necessary registers in the address space to 2 locations. The IPAC-X also provides a serial control interface (SCI).The FIFO size of the cyclic B-channel buffers is 128 bytes per channel and per direction, with programmable block size (threshold). Besides TE mode the S-transceiver supports other terminal relevant operation modes like line termination subscriber side (LT-S) and line termination trunk side (LT-T). A multi-line ISDN solution to support both S and U line coding is simplified as well as multi-line solution with up to 3 S-interfaces.An auxiliary I/O port has been added with interrupt capabilities on two input lines. These programmable I/O lines may be used to connect peripheral components to the IPAC-X which need software control or have to forward status information to the host. Three programmable LED outputs can be used to indicate certain status information, one of them is capable to indicate the activation status of the S-interface automatically. The IPAC-X is produced in advanced CMOS technology.

• Single chip host based ISDN solution
• Based on IPAC PSB 2115, integrating ISAC-S and HSCX-TE functionality
• 8-bit parallel microcontroller interface, Motorola and Siemens/Intel bus type multiplexed or non-multiplexed, direct-/indirect register addressing
• Serial control interface (SCI)
• Microcontroller access to all IOM-2 timeslots
• Various types of protocol support (Non-auto mode, transparent mode, extended transparent mode)
• B-channel HDLC controllers with 128 byte FIFOs
• Flexible access to 18-bit timeslots (2B+D) on IOM-2 for IDSL support
• D-channel HDLC controller with 64 byte FIFOs
• IOM-2 interface in TE, LT-T, LT-S and NT mode, single/double clocks and two strobe signals
• D-channel priority handler on IOM-2 for intelligent NT applications
• Monitor channel handler (master/slave)
• IOM-2 MONITOR and C/I-channel protocol to control peripheral devices
• Full duplex 2B+D S/T-interface transceiver according to ITU-T I.430
• Conversion of the frame structure between the S/T-interface and IOM-2
• Receive timing recovery
• D-channel access control
• Activation and deactivation procedures with automatic activation from power down state
• Access to S and Q bits of S/T-interface
• Adaptively switched receive thresholds
• Auxiliary Interface with general purpose I/O pins and LED drivers
• Two programmable timers
• Watchdog timer
• Test loops
• Sophisticated power management for restricted power mode
• Power supply 3.3 V
• 3.3 V output drivers, inputs are 5 V safe
• Advanced CMOS technology