ISDN S/T HDLC Interface 4-Line 192Kbps 3.3V 64-Pin MQFP

The ISDN Subscriber Access Controller ISAC-SX integrates a D-channel HDLC controller and a four wire S/T interface used to link voice/data terminals to the ISDN. It is based on the ISAC-S PEB 3086, and provides enhanced features and functionality. It includes the S-transceiver (Layer 1), an HDLC controller for the D-channel and one B-channel protocol controller (HDLC or transparent) with reduced features dedicated for firmware download via the B-channel. The system integration is simplified by several configurations of the parallel microcontroller interface selected via pin strapping. They include multiplexed and demultiplexed interface selection as well as the optional indirect register access mechanism which reduces the number of necessary registers in the address space to 2 locations. The ISAC-SX also provides a serial control interface (SCI). The FIFO size of the cyclic D-channel buffer is 64 bytes per direction with programmable block size (threshold). Besides TE mode the S-transceiver supports other terminal relevant operation modes like line termination subscriber side (LT-S), line termination trunk side (LT-T) and NT applications (NT, Intelligent NT mode). An auxiliary I/O port has been added with interrupt capabilities on two input lines. These programmable I/O lines may be used to connect peripheral components to the ISAC-SX which need software control or have to forward status information to the host. Three programmable LED outputs can be used to indicate certain status information, one of them is capable to indicate the activation status of the S-interface automatically. The ISAC-SX is produced in advanced CMOS technology.

• Full duplex 2B + D S/T interface transceiver according to ITU-T I.430
• Successor of ISAC-S PEB 2086 in 3.3 V technology
• 8-bit parallel microcontroller interface, Motorola and Siemens/Intel bus type multiplexed or non-multiplexed, direct-/indirect register addressing
• Serial control interface (SCI)
• Microcontroller access to all IOM-2 timeslots
• Various types of protocol support (Non-auto mode, transparent mode, extended transparent mode)
• One D-channel HDLC controller with 64 byte FIFOs per direction
• One B-channel HDLC controller with reduced functionality (e.g. for firmware upgrades)
• IOM-2 interface in TE, LT-T, LT-S and NT mode, single/double clocks and two strobe signals
• D-channel priority handler on IOM-2 for intelligent NT applications
• Monitor channel handler (master/slave)
• IOM-2 MONITOR and C/I-channel protocol to control peripheral devices
• Conversion of the frame structure between the S/T-interface and IOM-2
• Receive timing recovery
• D-channel access control
• Activation and deactivation procedures with automatic activation from power down state
• Access to S and Q bits of S/T-interface
• Adaptively switched receive thresholds
• Auxiliary Interface with general purpose I/O pins and LED drivers
• Two programmable timers
• Watchdog timer
• Software Reset
• Multiframe Synchronization
• Test loops
• Sophisticated power management for restricted power mode
• Power supply 3.3 V
• 3.3 V output drivers, inputs are 5 V safe
• Advanced CMOS technology