ISDN S/T HDLC Interface 1-Line 192Kbps 3.3V 64-Pin TQFP

The ISDN Subscriber Access Controller for Terminals ISAC-SX TE integrates a Dchannel HDLC controller and a four wire S/T interface used to link voice/data terminals to the ISDN. It is the successor of the ISAC-S TE PSB 2186 in 3.3 V technology. The system integration is simplified by several configurations of the parallel microcontroller interface selected via pin strapping. They include multiplexed and demultiplexed interface selection as well as the optional indirect register access mechanism which reduces the number of necessary registers in the address space to 2 locations. The ISAC-SX TE also provides a serial control interface (SCI). The FIFO size of the cyclic D-channel buffer is 64 bytes per direction with programmable block size (threshold). The S-transceiver supports terminals mode (TE), activation / deactivation, timing recovery and D-channel access control and priority control. One LED output which is capable to indicate the activation status of the S-interface automatically or can be programmed by the host. The ISAC-SX TE is produced in advanced CMOS technology. Full duplex 2B + D S/T interface transceiver according to ITU-T I.430 Successor of ISAC-S TE PSB 2186 in 3.3V technology 8-bit parallel microcontroller interface, Motorola and Siemens/Intel bus type multiplexed or non-multiplexed, direct-/indirect register addressing Serial control interface (SCI) Microcontroller access to all IOM-2 timeslots Various types of protocol support (Non-auto mode, transparent mode, extended transparent mode) D-channel HDLC controller with 2 x 64 byte FIFOs IOM-2 interface in TE mode, single/double clocks One serial data strobe signal (SDS) Monitor channel handler (master/slave) IOM-2 MONITOR and C/I-channel protocol to control peripheral devices Conversion of the frame structure between the S/T-interface and IOM-2 Receive timing recovery D-channel access control Activation and deactivation procedures with automatic activation from power down state Access to S and Q bits of S/T-interface Adaptively switched receive thresholds Two programmable timers Watchdog timer Software Reset One LED pin automatically indicating layer 1 activated state Test loops Sophisticated power management for restricted power mode Power supply 3.3 V 3.3 V output drivers, inputs are 5 V safe Advanced CMOS technology