ISDN CTLR HDLC S/T/U 8192Kbps 3.3V 100-Pin TQFP

The DELIC and VIP chipset realizes multiple ISDN S/T and Up interfaces together with controller functionality typically needed in PBX or Central Office systems. This functionality comprises voice channel handling, signaling control, layer-1 control, and even signal processing tasks. Moreover it provides a programmable master/slave clock generator with 2 PLLs, an universal µP interface and a DMA interface. DELIC-LC (PEB 20570) is a line card controller providing voice channel switching, multiple HDLC and layer-1 control for up to three VIPs (24 ISDN channels). Other transceiver ICs (32 analog or 16 digital channels) may additionally be connected via IOM-2/GCI interface. One IOM-2000 interface supporting three VIPs i.e. up to 24 ISDN channels Two IOM-2 (GCI) ports (configurable as PCM ports) supporting up to 16ISDN channels or 32 analog subscribers Four PCM ports with up to 4 x 2.048 Mbit/s (4 x 32 TS) or 2 x 4.096 Mbit/s or 1 x 8.192 Mbit/s Switching matrix 224 x 256 TS (8-bit switching) 24 HDLC controllers assignable to any D- or B-channel (at 16 kbit/s or 64 kbit/s) Serial communication controller: high-speed signaling channel for 2.048 Mbit/s Standard multiplexed and de-multiplexed µP interface: Siemens, Intel, Motorola Programmable PLL based Master/Slave clock generator, providing all system clocks from a single 16.384 MHz crystal source JTAG compliant test interface single 3.3 V power supply, 5 V tolerant inputs

Характеристики

Бренд Intel
Schedule B 8542390000
HTSN 8542390001
Страна происхождения United States
Operating 3.3 V
Supplier TQFP
Описание продукта 14 x 14 x 1.4 mm
Рабочая температура 0 to 70 °C
Data Rate 8192 Kbps
Reference S/T/U
Protocols HDLC
SKU: PEB 20570 F V3.1