ISDN CTLR HDLC S/T 8192Kbps 5V 44-Pin PLCC

The PEB 2054 (Extended PCM Interface Controller) is a highly integrated controller circuit optimized for analog and ISDN line card and central switches applications. The EPIC-1 provides the circuitry necessary to manage up to 32 digital (ISDN or proprietary) or 64 analog subscribers. The EPIC-1 is dedicated to switch PCM data between two serial interfaces, the system interface (PCM interface) and the configurable interface (CFI). The EPIC-1 performs non-blocking time and space switching for up to 128 channels. Since the system cost of the EPIC-1 is divided by the number of lines it controls, an highly economical implementation of digital or analog subscriber lines can be performed. The EPIC-S (PEB 2054) is a pin compatible device offering half the switching capacity of the EPIC-1. Therefore the EPIC-S is capable of handling up to 16 ISDN or 32 analog subscribers. It is programmable according to the EPIC-1 with respect of the pins not available. The EPIC is implemented in a Siemens advanced CMOS-technology and manufactured in a P-LCC-44-1 package. The EPIC is member of a chip family supporting a highly economical implementation of line cards and subscriber terminals.

• Board Controller for up to
  • – 16 ISDN or 32 analog subscribers (PEB 2054)
• Non-blocking switch for
  • 64 channels (PEB 2054)
• Switching of 16-, 32-, or 64-kbit/s channels
• Two consecutive 64-kbit/s channels can be switched as a single 128-kbit/s channel
• Freely programmable time slot assignment for all subscribers
• Two serial interfaces (PCM and CFI) programmable over a wide data range (128 - 8192 kbit/s)
• Data rates of PCM and configurable interface independent from each other (data rate adaptation)
• PCM-interface
  • Tristate control signals for external drivers
  • Programmable clock shift
  • Single or double data clock
• Configurable interface
  • Configurable for IOM-, SLD- and PCM-applications
  • High degree of flexibility for datastream adaptation
  • Programmable clockshift
  • Single or double data clock
• Synchronous µP-access to two selected channels