Framer T1/E1/J1 3.3V 256-Pin CSBGA

The DS26401 is an octal, software-selectable T1, E1, or J1 framer. It is composed of 8 framer/formatters and a system (backplane) interface. Each framer has an HDLC controller that can be mapped to any DS0 or FDL (T1)/Sa (E1) bit. The DS26401 also includes a full-feature BERT device, which can be used with any of the 8 T1/E1 ports, and an internal clock adapter useful for creating synchronous, high-frequency backplane timing. The DS26401 is controlled through an 8-bit parallel port that can be configured for nonmultiplexed Intel or Motorola operation.

• 8 Independent, Full-Featured T1/E1/J1 Framers/Formatters
• Independent Transmit and Receive Paths
• Flexible Signaling Extraction and Insertion
• Alarm Detection and Insertion
• Transmit Synchronizer
• AMI, B8ZS, HDB3, NRZ Line Coding
• Performance Monitor Counters
• BOC Message Controller (T1)
• Two-Frame Elastic Store Buffers for Each Transmitter and Receiver
• One HDLC Controller per Framer
• RAI-CI and AIS-CI Support
• Full-Feature BERT can be Mapped to Any Port
• Flexible TDM Backplane Supports Bus Rates from 1.544MHz to 16.384MHz
• Internal Clock Generator (CLAD) Supplies 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
• JTAG Test Port
• Single 3.3V Supply with 5V Tolerant Inputs
• 17mm x 17mm, 256-Pin BGA (1.00mm Pitch)