Framer E1/J1/T1 3.3V 256-Pin CSBGA

The DS26556 is a quad, software-selectable T1, E1, or J1 transceiver with a cell/packet/TDM interface. It is composed of four framer/formatters + LIUs, and a UTOPIA (cell), POS-PHY (packet), and TDM backplane interface. Each framer has an HDLC controller that can be mapped to any DS0 or FDL (T1)/Sa (E1) bit. The DS26556 also includes full-featured BERT devices per port, and an internal clock adapter useful for creating synchronous, high-frequency backplane timing. The DS26556 is controlled through an 8-bit parallel port that can be configured for nonmultiplexed Intel or Motorola operation.

• Four Independent, Full-Featured T1/E1/J1 Transceivers
• UTOPIA 2 and 3 Cell Interface
• POS-PHY 2 and 3 Packet Interface
• TDM Backplane Supports TDM Bus Rates from 1.544MHz to 16.384MHz
• Alarm Detection and Insertion
• Full-Featured BERT for Each Port
• AMI, B8ZS, HDB3, NRZ Line Coding
• Transmit Synchronizer
• BOC Message Controller (T1)
• One HDLC Controller per Framer
• Performance Monitor Counters
• RAI-CI and AIS-CI Support
• Internal Clock Generator (CLAD) Supplies 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
• JTAG Test Port
• Single 3.3V Supply with 5V Tolerant Inputs
• 17mm x 17mm, 256-Pin BGA (1.00mm Pitch)