Framer E1/J1/T1 3.3V 208-Pin BGA

The IDT82V2048E can be configured as an octal T1, octal E1 or octal J1 Line Interface Unit. The IDT82V2048E performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and detects and reports the LOS conditions. An integrated Adaptive Equalizer is available to increase the receive sensitivity and enable programming of LOS levels. In transmit path, there is an AMI/B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter Attenuator for each channel, which can be placed in either the receive path or the transmit path. The Jitter Attenuator can also be disabled. The IDT82V2048E supports both Single Rail and Dual Rail system interfaces and both serial and parallel control interfaces. To facilitate the network maintenance, a PRBS/QRSS generation/detection circuit is integrated in each channel, and different types of loopbacks can be set on a per channel basis. Four different kinds of line terminating impedance, 75?, 100 ?, 110 ? and 120 ? are selectable on a per channel basis. The chip also provides driver short-circuit protection and supports JTAG boundary scanning. The IDT82V2048E can be used in SDH/SONET, LAN, WAN, Routers, Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices, CSU/DSU equipment, etc.

• Eight channel T1/E1/J1 short haul line interfaces
• Supports HPS (Hitless Protection Switching) for 1+1 protection without external relays
• Programmable T1/E1/J1 switchability allowing one bill of material for any line condition
• Single 3.3 V power supply with 5 V tolerance on digital interfaces
• Adaptive receive sensitivity up to -20 dB ï Non-intrusive monitoring per ITU G.772 specification
• Short circuit protection for line drivers
• LOS (Loss Of Signal) detection with programmable LOS levels
• AIS (Alarm Indication Signal) detection
• JTAG interface
• Supports serial control interface, Motorola and Intel Non-Multiplexed interfaces
• Package: 208-pin PBGA