Framer E1/J1/T1 1.8V/3.3V 256-Pin BGA

The DS33R11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over a T1/E1/J1 data stream. The device performs store-and-forward of packets with full wire-speed transport capability. The built-in Committed Information Rate (CIR) Controller provides fractional bandwidth allocation up to the line rate in increments of 512kbps. The DS33R11 can operate with an inexpensive external processor.

• 10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control
• Integrated T1/E1/J1 Framer and LIU
• HDLC/LAPS Encapsulation with Programmable FCS and Interframe Fill
• Committed Information Rate Controller Provides Fractional Allocations in 512kbps Increments
• Programmable BERT for Serial (TDM) Interface
• External 16MB, 100MHz SDRAM Buffering
• Parallel Microprocessor Interface
• 1.8V, 3.3V Supplies
• Reference Design Routes on Two Signal Layers
• IEEE 1149.1 JTAG Support