DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin TSOP-II

The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134, 217, 728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33, 554, 432-bit banks is organized as 4,096 rows by 512 columns by 16 bits.Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto pre-charge function may be enabled to provide a self-timed row pre-charge that is initiated at the end of the burst sequence.The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of pre-fetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random operation. Pre-charging one bank while accessing one of the other three banks will hide the pre-charge cycles and provide seamless, high-speed, random-access operation.The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.

• Full Military temp (-55°C to 125°C) processing available
• Configuration: 8 Meg x 16 (2 Meg x 16 x 4 banks)
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge, includes CONCURRENT AUTO PRECHARGE and Auto Refresh Modes
• Self Refresh Mode (IT & ET)
• 64ms, 4,096-cycle refresh (IT)
• 24ms 4,096 cycle refresh (XT)
• WRITE Recovery (tWR = “2 CLK”)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply