Описание
The MCF52256 device) is a member of the ColdFire family of reduced instruction set computing (RISC) microprocessors. This 32-bit device is based on the Version 2 ColdFire core operating at a frequency up to 80 MHz, offering high performance and low power consumption. On-chip memories connected tightly to the processor core include up to 512 KB of flash memory and 64 KB of static random access memory (SRAM)
- Version 2 ColdFire variable-length RISC processor core
- Static operation
- 32-bit address and data paths on-chip
- Up to 80 MHz processor core frequency
- Sixteen general-purpose, 32-bit data and address registers
- Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions for improved bit processing (ISA_A+)
- Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16×16 – 32 or 32×32 – 48 operations
- Illegal instruction decode that allows for 68-Kbyte emulation support
- System debug support
- Real-time trace for determining dynamic execution path
- Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
- Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or 2-level trigger
- On-chip memories
- 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply support
- 256 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses
- Power management
- Fully static operation with processor sleep and whole chip stop modes
- Rapid response to interrupts from the low-power sleep mode (wake-up feature)
- Clock enable/disable for each peripheral when not used
- FlexCAN 2.0B module
- Based on and includes all existing features of the Freescale TouCAN module
- Full implementation of the CAN protocol specification version 2.0B
- Standard data and remote frames (up to 109 bits long)
- Extended data and remote frames (up to 127 bits long)
- Zero to eight bytes data length
- Programmable bit rate up to 1 Mbit/sec
- Flexible message buffers (MBs), totaling up to 16 message buffers of 0–8 byte data length each, configurable as Rx or Tx, all supporting standard and extended messages
- Unused MB space can be used as general purpose RAM space
- Listen-only mode capability
- Content-related addressing
- No read/write semaphores
- Three programmable mask registers: global for MBs 0-13, special for MB14, and special for MB15
- Programmable transmit-first scheme: lowest ID or lowest buffer number -Time stamp based on 16-bit free-running timer
- Global network time, synchronized by a specific message
- Maskable interrupts
- Three universal asynchronous/synchronous receiver transmitters (UARTs)
- 16-bit divider for clock generation
- Interrupt control logic with maskable interrupts
- DMA support
- Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity
- Up to two stop bits in 1/16 increments
- Error-detection capabilities
- Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
- Transmit and receive FIFO buffers
- I2C module
- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
- Fully compatible with industry-standard I2 C bus
- Master and slave modes support multiple masters
- Queued serial peripheral interface (QSPI)
- Full-duplex, three-wire synchronous transfers
- Up to four chip selects available
- Master mode operation only
- Programmable bit rates up to half the CPU clock frequency
- Up to 16 pre-programmed transfers
- Fast ADC
- Eight analog input channels
- 12-bit resolution
- Minimum 1.125 μs conversion time
- Simultaneous sampling of two channels for motor control applications
- Single-scan or continuous operation
