Clock Driver 2-IN HSTL 64-Pin LQFP EP T/R

The NB100EP223 is a low skew 2:1:22 differential bus clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are differential HSTL or LVPECL and they are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous so that the outputs will only be enabled/disabled when they are already in LOW state.The NB100EP223 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. In any differential output pair, the same bias andtermination scheme is required. Unused output pairs should be left unterminated (open) to reduce power and switching noise as much as possible. Any unused single line of a differential pair should be terminated the same as the used line to maintain balanced loads on the differential driver outputs. The output structure uses an open emitter architecture and will be terminated with 50 to ground instead of a standard HSTL configuration.The wide VIHCMR specification allows both pair of CLOCK inputs to accept LVDS levels.

• 100 ps Typical Device-to-Device Skew
• 25 ps Typical Within Device Skew
• HSTL Outputs Drive 50O to Ground With No Offset Voltage
• Maximum Frequency > 500 Mhz
• 1 ns Typical Propagation Delay
• LVPECL and HSTL Mode Operating Range: V_CC = 3 V to 3.6 V with GND = 0 V, V_CCO = 1.6 V to 2.0 V
• Q Output will Default Low with Inputs Open
• Thermally Enhanced 64-Lead LQFP
• CLOCK Inputs are LVDS-Compatible; Requires External 100 O LVDS Termination Resistor