Audio Codec 2ADC /2 DAC 24-Bit 32-Pin QFN T/R, WM8904CGEFL/RV, Cirrus Logic

The WM8804 is a high performance consumer mode S/PDIF transceiver with support for 1 received channel and 1 transmitted channel. A crystal derived, or externally provided high quality master clock is used to allow low jitter recovery of S/PDIF supplied master clocks. Generation of all typically used audio clocks is possible using the high performance internal PLL. A dedicated CLKOUT pin provides a high drive clock output. A pass through option is provided which allows the device simply to be used to clean up (de-jitter) the received digital audio signals. The device may be used under software control or stand alone hardware control modes. In software control mode, both two-wire with read back and three-wire interface modes are supported. Status and error monitoring is built-in and results can be read back over the control interface, on the GPO pins or streamed over the audio data interface in ‘With Flags’ mode (audio data with status flags appended). The audio data interface supports I²S, left justified, right justified and DSP audio formats of 16-24 bit word length, with sample rates from 32 to 192ks/s. The device is supplied in a 20-lead Pb-free SSOP package.

  • S/PDIF (IEC60958-3) compliant
  • Advanced jitter attenuating PLL with low intrinsic period jitter of 50 ps RMS
  • S/PDIF recovered clock using PLL, or stand alone crystal derived clock generation
  • Supports 10 – 27MHz crystal clock frequencies
  • two-wire / three-wire serial or hardware control interface
  • Programmable audio data interface modes:
    • I²S, Left, Right Justified or DSP
    • 16/20/24 bit word lengths
  • 1 channel receiver input and 1 channel transmit output
  • Auto frequency detection / synchronisation
  • Selectable output status data bits
  • Up to 3 configurable GPO pins
  • De-emphasis flag output
  • Non-audio detection including DOLBYTM and DTSTM
  • Channel status changed flag
  • Configurable clock distribution with selectable output MCLK rate of 512fs, 256fs, 128fs and 64fs
  • 2.7 to 3.6V digital and PLL supply voltages
  • 20-lead SSOP package

Характеристики

Бренд

Operating_supply_voltage

1, 1.8 V

Eccn

EAR99

Htsn

8542390001

Kind

PCM

Max_processing_temp

260

Mounting

Surface Mount

Msl_level

3

Number_of_adcs

2

Количество каналов

2ADC /2 DAC

Number_of_dacs

2

Operating_temperature

-40 to 85 °C

Number_of_dac_outputs

2

Pin_count

32

Product_dimensions

4 x 4 x 0.715

Sampling_rate

96 ksps

Schedule_b

8542390000

Screening_level

Industrial

Specifications

https://4donline.ihs.com/images/VipMasterIC/IC/CIRR/CIRR-S-A0005304666/CIRR-S-A0005304666-1.pdf?hkey=52A5661711E402568146F3353EA87419

Supplier_package

QFN

Number_of_adc_inputs

3

Adc_dac_resolution

24 Bit

Country_of_origin

Taiwan

Артикул: WM8904CGEFL/RV

Описание

The WM8804 is a high performance consumer mode S/PDIF transceiver with support for 1 received channel and 1 transmitted channel. A crystal derived, or externally provided high quality master clock is used to allow low jitter recovery of S/PDIF supplied master clocks. Generation of all typically used audio clocks is possible using the high performance internal PLL. A dedicated CLKOUT pin provides a high drive clock output. A pass through option is provided which allows the device simply to be used to clean up (de-jitter) the received digital audio signals. The device may be used under software control or stand alone hardware control modes. In software control mode, both two-wire with read back and three-wire interface modes are supported. Status and error monitoring is built-in and results can be read back over the control interface, on the GPO pins or streamed over the audio data interface in ‘With Flags’ mode (audio data with status flags appended). The audio data interface supports I²S, left justified, right justified and DSP audio formats of 16-24 bit word length, with sample rates from 32 to 192ks/s. The device is supplied in a 20-lead Pb-free SSOP package.

  • S/PDIF (IEC60958-3) compliant
  • Advanced jitter attenuating PLL with low intrinsic period jitter of 50 ps RMS
  • S/PDIF recovered clock using PLL, or stand alone crystal derived clock generation
  • Supports 10 – 27MHz crystal clock frequencies
  • two-wire / three-wire serial or hardware control interface
  • Programmable audio data interface modes:
    • I²S, Left, Right Justified or DSP
    • 16/20/24 bit word lengths
  • 1 channel receiver input and 1 channel transmit output
  • Auto frequency detection / synchronisation
  • Selectable output status data bits
  • Up to 3 configurable GPO pins
  • De-emphasis flag output
  • Non-audio detection including DOLBYTM and DTSTM
  • Channel status changed flag
  • Configurable clock distribution with selectable output MCLK rate of 512fs, 256fs, 128fs and 64fs
  • 2.7 to 3.6V digital and PLL supply voltages
  • 20-lead SSOP package

Детали

Бренд

Operating_supply_voltage

1, 1.8 V

Eccn

EAR99

Htsn

8542390001

Kind

PCM

Max_processing_temp

260

Mounting

Surface Mount

Msl_level

3

Number_of_adcs

2

Количество каналов

2ADC /2 DAC

Number_of_dacs

2

Operating_temperature

-40 to 85 °C

Number_of_dac_outputs

2

Pin_count

32

Product_dimensions

4 x 4 x 0.715

Sampling_rate

96 ksps

Schedule_b

8542390000

Screening_level

Industrial

Specifications

https://4donline.ihs.com/images/VipMasterIC/IC/CIRR/CIRR-S-A0005304666/CIRR-S-A0005304666-1.pdf?hkey=52A5661711E402568146F3353EA87419

Supplier_package

QFN

Number_of_adc_inputs

3

Adc_dac_resolution

24 Bit

Country_of_origin

Taiwan