ATM UNI Single 2.048Mbps 3.3V 256-Pin BGA T/R

The Interworking Element for 8 E1/T1 Lines PXB 4220E is a member of ATM chip set. Together with framing and line interface components (e.g. Infineon’s QuadFALC PEB 22554) the IWE8 serves as gateway between Asynchronous Transfer Mode (ATM) networks and timeslot based PDH networks. Full duplex ATM Packetizer/Depacketizer for 8 E1/T1 highways Configurable to T1 or E1 mode via external pin 8 T1/E1 ports configurable independently to ATM or AAL Mode ATM Mode: ATM cell mapping into PDH according to ITUT G.804 B-ISDN User-Network interface - Physical Layer according to ITU-T I.432 B-ISDN User-Network interface - Physical Layer operation at 1544 KBit/s and 2048 KBit/s according to ITU-T I.432.3 AAL Mode: AAL1 according to ITU-T I.363.1 or transparent without any adaptation layer overhead (AAL0) T1/E1 unstructured service according to ATM Forum af-vtoa-0078.000 Structured T1/E1 N x 64 kbit/s service with M channels of N x 64 kbit/s (M, N = 1to 24 for T1) (M, N = 1to 32 for E1) Channel Associated Signaling (CAS) support Echo Canceller Mode Partially filled cells with programmable filling thresholds Selectable Sequence Count Algorithm: Robust/Fast according to ITU-T I.363.1 According to ETSI Fast: Saves 6 ms during reassembly for 1 x 64 kbit/s connection AAL0 option: 48 Bytes user payload per ATM Cell, without AAL overhead Reassembly buffer can compensate up to +/- 4 ms Cell Delay Variation (CDV) Statistics counters per channel for lost/misinserted/errored cells etc