ADC Quad Delta-Sigma 48ksps 24-bit Serial 32-Pin QFN EP Rail, CS53L30-CNZ, Cirrus Logic

The CS53L30 is a high-performance, low-power, quad-channel ADC. It is designed for use in multiple-mic applications while consuming minimal board space and power. The flexible ADC inputs can accommodate four channels of analog mic or line-input data in differential, pseudo differential, or single-ended mode, or four channels of digital mic data. The analog input path includes a +10- to +20-dB boost and a –6- to +12-dB PGA. Digital mic data bypasses the analog gain circuits and is fed directly to the decimators. Four mic bias generators are integrated into the device. The device also includes two digital mic serial clock outputs. The CS53L30 includes several digital signal processing features such as high-pass filters, noise gate, and volume control. The device can output its four channels of audio data over two I2S ports or a single TDM port. Additionally, up to four CS53L30s can be used to output up to 16 channels of data over a single TDM line. This is done by setting the appropriate frame slots for each device, and each device then alternates between outputting data and setting the output pin to high impedance. The CS53L30 can operate as a serial port clock master or slave. In Master Mode, clock dividers are used to generate the internal master clock and audio clocks from either the 6-/12-MHz, 6.144-/12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master clock. The device is powered from VA, a 1.8-V nominal supply and VP, a typical battery supply. An internal LDO on the VA supply powers the device’s digital core. The VP supply powers the mic bias generators and the AFE. The CS53L30 is controlled by an I2C control port. A reset pin is also included. The device is available in a 30-ball 0.4-mm pitch WLCSP package and 32-pin 5 x 5-mm QFN package.

  • 91-dB dynamic range (A-weighted) @ 0-dB gain
  • –84-dB THD+N @ 0-dB gain
  • Four fully differential inputs: Four analog mic/line inputs
  • Four analog programmable gain amplifiers
  • –6 to +12 dB, in 0.5-dB steps
  • +10 or +20 dB boost for mic input
  • Four mic bias generators
  • MUTE pin for quick mic mute and programmable quick power down

Характеристики

Number_of_analog_inputs

4

Digital_supply_support

Yes

Architecture

Delta-Sigma

Resolution

24 Bit

Бренд

Msl_level

3

Eccn

EAR99

Htsn

8542390001

Mounting

Surface Mount

Pin_count

32

Product_dimensions

5 x 5 x 0.95(Max)

Schedule_b

8542390000

Specifications

https://4donline.ihs.com/images/VipMasterIC/IC/CIRR/CIRR-S-A0009698965/CIRR-S-A0009698965-1.pdf?hkey=52A5661711E402568146F3353EA87419

Number_of_adc_channels

4

Operating_supply_volt

1.71, 1.8/3.3, 1.8/5 V, 1.89/5.25, 3

Number_of_adcs

4

Артикул: CS53L30-CNZ

Описание

The CS53L30 is a high-performance, low-power, quad-channel ADC. It is designed for use in multiple-mic applications while consuming minimal board space and power. The flexible ADC inputs can accommodate four channels of analog mic or line-input data in differential, pseudo differential, or single-ended mode, or four channels of digital mic data. The analog input path includes a +10- to +20-dB boost and a –6- to +12-dB PGA. Digital mic data bypasses the analog gain circuits and is fed directly to the decimators. Four mic bias generators are integrated into the device. The device also includes two digital mic serial clock outputs. The CS53L30 includes several digital signal processing features such as high-pass filters, noise gate, and volume control. The device can output its four channels of audio data over two I2S ports or a single TDM port. Additionally, up to four CS53L30s can be used to output up to 16 channels of data over a single TDM line. This is done by setting the appropriate frame slots for each device, and each device then alternates between outputting data and setting the output pin to high impedance. The CS53L30 can operate as a serial port clock master or slave. In Master Mode, clock dividers are used to generate the internal master clock and audio clocks from either the 6-/12-MHz, 6.144-/12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master clock. The device is powered from VA, a 1.8-V nominal supply and VP, a typical battery supply. An internal LDO on the VA supply powers the device’s digital core. The VP supply powers the mic bias generators and the AFE. The CS53L30 is controlled by an I2C control port. A reset pin is also included. The device is available in a 30-ball 0.4-mm pitch WLCSP package and 32-pin 5 x 5-mm QFN package.

  • 91-dB dynamic range (A-weighted) @ 0-dB gain
  • –84-dB THD+N @ 0-dB gain
  • Four fully differential inputs: Four analog mic/line inputs
  • Four analog programmable gain amplifiers
  • –6 to +12 dB, in 0.5-dB steps
  • +10 or +20 dB boost for mic input
  • Four mic bias generators
  • MUTE pin for quick mic mute and programmable quick power down

Детали

Number_of_analog_inputs

4

Digital_supply_support

Yes

Architecture

Delta-Sigma

Resolution

24 Bit

Бренд

Msl_level

3

Eccn

EAR99

Htsn

8542390001

Mounting

Surface Mount

Pin_count

32

Product_dimensions

5 x 5 x 0.95(Max)

Schedule_b

8542390000

Specifications

https://4donline.ihs.com/images/VipMasterIC/IC/CIRR/CIRR-S-A0009698965/CIRR-S-A0009698965-1.pdf?hkey=52A5661711E402568146F3353EA87419

Number_of_adc_channels

4

Operating_supply_volt

1.71, 1.8/3.3, 1.8/5 V, 1.89/5.25, 3

Number_of_adcs

4