ADC Dual Pipelined 200Msps 10-bit Parallel/LVDS 60-Pin LLP EP T/R, ADC10DV200CISQE/NOPB, Texas Instruments

The ADC10DV200 is a monolithic analog-to-digital converter capable of converting two analog input signals into 10-bit digital words at rates up to 200 Mega Samples Per Second (MSPS). The digital output mode is selectable and can be either differential LVDS or CMOS signals. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 900MHz. Fabricated in core CMOS process, the ADC10DV200 may be operated from a single 1.8V power supply. The ADC10DV200 achieves approximately 9.6 effective bits at Nyquist and consumes just 280mW at 170MSPS in CMOS mode and 450mW at 200MSPS in LVDS mode. The power consumption can be scaled down further by reducing sampling rates. 

  • Single 1.8V Power Supply Operation.
  • Power Scaling with Clock Frequency.
  • Internal Sample-and-Hold.
  • Internal or External Reference.
  • Power Down Mode.
  • Offset Binary or 2"s Complement Output Data Format.
  • LVDS or CMOS Output Signals.
  • 60-pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)
  • Clock Duty Cycle Stabilizer.
  • IF Sampling Bandwidth > 900MHz.
  • Resolution 10 Bits
  • Conversion Rate 200 MSPS
  • ENOB 9.6 bits (typ) @Fin=70 MHz
  • SNR 59.9 dBFS (typ) @Fin=70 MHz
  • SINAD 59.9 dBFS (typ) @Fin=70 MHz
  • SFDR 82 dBFS (typ) @Fin=70 MHz
  • LVDS Power 450mW (typ) @Fs=200 MSPS
  • CMOS Power 280mW (typ) @Fs=170 MSPS
  • Operating Temp. Range -40°C to +85°C.
  • Характеристики

    Volt_supply_source

    Analog and Digital

    Number_of_analog_inputs

    2

    Sampling_rate

    200 Msps

    Volt_reference

    External, Internal

    Digital_supply_support

    Yes

    Architecture

    Pipelined

    Resolution

    10 Bit

    Differential_nonlinearity

    0.43 LSB

    Signal_to_noise_ratio

    59.9 dBFS

    Input_type

    Voltage

    Input_signal_type

    Differential

    Input_volt

    1.5 Vp-p

    Бренд

    Msl_level

    3

    Country_of_origin

    United States

    Eccn

    EAR99

    Htsn

    8542390001

    Lead_finish

    Tin

    Max_processing_temp

    260

    Mounting

    Surface Mount

    Operating_temp

    -40 to 85 °C

    Pin_count

    60

    Product_dimensions

    9 x 9 x 0.8 mm

    Schedule_b

    8542390000

    Screening_level

    Industrial

    Specifications

    http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=ADC10DV200&&fileType=pdf

    Supplier_package

    LLP EP

    Operating_supply_volt

    1.7, 1.8 V, 1.9

    Number_of_adcs

    2

    Digital_interface_type

    LVDS, Parallel

    Артикул: ADC10DV200CISQE/NOPB

    Описание

    The ADC10DV200 is a monolithic analog-to-digital converter capable of converting two analog input signals into 10-bit digital words at rates up to 200 Mega Samples Per Second (MSPS). The digital output mode is selectable and can be either differential LVDS or CMOS signals. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 900MHz. Fabricated in core CMOS process, the ADC10DV200 may be operated from a single 1.8V power supply. The ADC10DV200 achieves approximately 9.6 effective bits at Nyquist and consumes just 280mW at 170MSPS in CMOS mode and 450mW at 200MSPS in LVDS mode. The power consumption can be scaled down further by reducing sampling rates. 

  • Single 1.8V Power Supply Operation.
  • Power Scaling with Clock Frequency.
  • Internal Sample-and-Hold.
  • Internal or External Reference.
  • Power Down Mode.
  • Offset Binary or 2"s Complement Output Data Format.
  • LVDS or CMOS Output Signals.
  • 60-pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)
  • Clock Duty Cycle Stabilizer.
  • IF Sampling Bandwidth > 900MHz.
  • Resolution 10 Bits
  • Conversion Rate 200 MSPS
  • ENOB 9.6 bits (typ) @Fin=70 MHz
  • SNR 59.9 dBFS (typ) @Fin=70 MHz
  • SINAD 59.9 dBFS (typ) @Fin=70 MHz
  • SFDR 82 dBFS (typ) @Fin=70 MHz
  • LVDS Power 450mW (typ) @Fs=200 MSPS
  • CMOS Power 280mW (typ) @Fs=170 MSPS
  • Operating Temp. Range -40°C to +85°C.
  • Детали

    Volt_supply_source

    Analog and Digital

    Number_of_analog_inputs

    2

    Sampling_rate

    200 Msps

    Volt_reference

    External, Internal

    Digital_supply_support

    Yes

    Architecture

    Pipelined

    Resolution

    10 Bit

    Differential_nonlinearity

    0.43 LSB

    Signal_to_noise_ratio

    59.9 dBFS

    Input_type

    Voltage

    Input_signal_type

    Differential

    Input_volt

    1.5 Vp-p

    Бренд

    Msl_level

    3

    Country_of_origin

    United States

    Eccn

    EAR99

    Htsn

    8542390001

    Lead_finish

    Tin

    Max_processing_temp

    260

    Mounting

    Surface Mount

    Operating_temp

    -40 to 85 °C

    Pin_count

    60

    Product_dimensions

    9 x 9 x 0.8 mm

    Schedule_b

    8542390000

    Screening_level

    Industrial

    Specifications

    http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=ADC10DV200&&fileType=pdf

    Supplier_package

    LLP EP

    Operating_supply_volt

    1.7, 1.8 V, 1.9

    Number_of_adcs

    2

    Digital_interface_type

    LVDS, Parallel