ADC Dual Pipelined 125Msps 14-bit Serial (1-Wire, 2-Wire)/LVDS 48-Pin VQFN EP T/R, ADS6245IRGZT, Texas Instruments

ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.ADS624X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C).

  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • Simultaneous Sample and Hold
  • 3.5 dB Coarse Gain and up to 6 dB Programmable
    Fine Gain for SFDR/SNR Trade-Off
  • Serialized LVDS Outputs with Programmable
    Internal Termination Option
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs
    and Amplitude down to 400 mVpp
  • Internal Reference with External Reference
    Support
  • No External Decoupling Required for References
  • 3.3-V Analog and Digital Supply
  • 48 QFN Package (7 mm × 7 mm)
  • Pin Compatible 12-Bit Family (ADS622X – SLAS543A)
  • Feature Compatible Quad Channel Family
    (ADS644X – SLAS531A and ADS642X – SLAS532A)
  • Характеристики

    Volt_supply_source

    Single

    Country_of_origin

    United States

    Sampling_rate

    125 Msps

    Volt_reference

    External, Internal

    Digital_supply_support

    No

    Architecture

    Pipelined

    Resolution

    14 Bit

    Typical_power_dissipation

    1000 mW

    Differential_nonlinearity

    -0.95, 2.5 LSB

    Signal_to_noise_ratio

    73.7 dBFS

    Input_type

    Voltage

    Input_signal_type

    Differential

    Input_volt

    2 Vp-p

    Бренд

    Msl_level

    3

    Number_of_analog_inputs

    2

    Htsn

    8542390001

    Eccn

    3A991.C.3

    Lead_finish

    Gold

    Max_power_dissipation

    1200 mW

    Max_processing_temp

    260

    Mounting

    Surface Mount

    Operating_temp

    -40 to 85 °C

    Pin_count

    48

    Product_dimensions

    7 x 7 x 0.9 mm

    Schedule_b

    8542390000

    Screening_level

    Industrial

    Specifications

    http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=ADS6242&&fileType=pdf

    Supplier_package

    VQFN EP

    Operating_supply_volt

    3, 3.3 V, 3.6

    Number_of_adcs

    2

    Digital_interface_type

    LVDS, Serial (1-Wire, 2-Wire)

    Артикул: ADS6245IRGZT

    Описание

    ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.ADS624X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C).

  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • Simultaneous Sample and Hold
  • 3.5 dB Coarse Gain and up to 6 dB Programmable
    Fine Gain for SFDR/SNR Trade-Off
  • Serialized LVDS Outputs with Programmable
    Internal Termination Option
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs
    and Amplitude down to 400 mVpp
  • Internal Reference with External Reference
    Support
  • No External Decoupling Required for References
  • 3.3-V Analog and Digital Supply
  • 48 QFN Package (7 mm × 7 mm)
  • Pin Compatible 12-Bit Family (ADS622X – SLAS543A)
  • Feature Compatible Quad Channel Family
    (ADS644X – SLAS531A and ADS642X – SLAS532A)
  • Детали

    Volt_supply_source

    Single

    Country_of_origin

    United States

    Sampling_rate

    125 Msps

    Volt_reference

    External, Internal

    Digital_supply_support

    No

    Architecture

    Pipelined

    Resolution

    14 Bit

    Typical_power_dissipation

    1000 mW

    Differential_nonlinearity

    -0.95, 2.5 LSB

    Signal_to_noise_ratio

    73.7 dBFS

    Input_type

    Voltage

    Input_signal_type

    Differential

    Input_volt

    2 Vp-p

    Бренд

    Msl_level

    3

    Number_of_analog_inputs

    2

    Htsn

    8542390001

    Eccn

    3A991.C.3

    Lead_finish

    Gold

    Max_power_dissipation

    1200 mW

    Max_processing_temp

    260

    Mounting

    Surface Mount

    Operating_temp

    -40 to 85 °C

    Pin_count

    48

    Product_dimensions

    7 x 7 x 0.9 mm

    Schedule_b

    8542390000

    Screening_level

    Industrial

    Specifications

    http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=ADS6242&&fileType=pdf

    Supplier_package

    VQFN EP

    Operating_supply_volt

    3, 3.3 V, 3.6

    Number_of_adcs

    2

    Digital_interface_type

    LVDS, Serial (1-Wire, 2-Wire)