FIFO Mem Sync Dual Width Uni-Dir 256 x 18 56-Pin SSOP Tube

The SN74ALVC7805 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access times. This device is designed for 3-V to 3.6-V VCC operation. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET) must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ALVC7805 is characterized for operation from 0°C to 70°C.

Member of the Texas Instruments Widebus^TM Family

Low-Power Advanced CMOS Technology

Operates From 3-V to 3.6-V V_CC

Free-Running Read and Write Clocks Can Be Asynchronous or Coincident

Read and Write Operations Synchronized to Independent System Clocks

Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag

Bidirectional Configuration and Width Expansion Without Additional Logic

Input-Ready Flag Synchronized to Write Clock

Output-Ready Flag Synchronized to Read Clock

Fast Access Times of 13 ns With a 50-pF Load and All Data Outputs Switching Simultaneously

Data Rates up to 50 MHz

Pin-to-Pin Compatible With SN74ACT7803, SN74ACT7805, and SN74ACT7813

Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Lead Spacing