NOR Flash Parallel 3V/3.3V 512Mbit 64M/32M x 8bit/16bit 100ns 64-Pin BGA Tray

The device is an asynchronous, uniform block, parallel NOR Flash memory device. READ, ERASE, and PROGRAM operations are performed using a single low-voltage supply. Upon power-up, the device defaults to read array mode. The main memory array is divided into uniform blocks that can be erased independently so that valid data can be preserved while old data is purged. PROGRAM and ERASE commands are written to the command interface of the memory. An on-chip program/ erase controller simplifies the process of programming or erasing the memory by taking care of all special operations required to update the memory contents. The end of a PROGRAM or ERASE operation can be detected and any error condition can be identified. The command set required to control the device is consistent with JEDEC standards. CE#, OE#, and WE# control the bus operation of the device and enable a simple connection to most microprocessors, often without additional logic. The device supports asynchronous random read and page read from all blocks of the array. It also features an internal program buffer that improves throughput by programming 512 words via one command sequence. A 128-word extended memory block overlaps addresses with array block 0. Users can program this additional space and then protect it to permanently secure the contents. The device also features different levels of hardware and software protection to secure blocks from unwanted modification.

• 2Gb = stacked device (two 1Gb die)
• Supply voltage
  • VCC = 2.7–3.6V (program, erase, read)
  • VCCQ = 1.65–VCC (I/O buffers)
• Asynchronous random/page read
  • Page size: 16 words or 32 bytes
  • Page access: 25ns
  • Random access: 100ns (Fortified BGA); 110ns (TSOP)
• Buffer program: 512-word program buffer
• Program time
  • 0.88µs per byte (1.14 MB/s) TYP when using full 512-word buffer size in buffer program
• Memory organization
  • Uniform blocks: 128-Kbytes or 64-Kwords each
• Program/erase controller
  • Embedded byte (x8)/word (x16) program algorithms
• Program/erase suspend and resume capability
  • Read from another block during a PROGRAM SUSPEND operation
  • Read or program another block during an ERASE SUSPEND operation
• BLANK CHECK operation to verify an erased block
• Unlock bypass, block erase, chip erase, and write to buffer capability
  • Fast buffered/batch programming
  • Fast block/chip erase
• VPP/WP# pin protection
  • Protects first or last block regardless of block protection settings
• Software protection
  • Volatile protection
  • Nonvolatile protection
  • Password protection
  • Password access
• Extended memory block
  • 128-word (256-byte) block for permanent, secure identification
  • Programmed or locked at the factory or by the customer
• Low power consumption: Standby mode
• JESD47-compliant
  • 100,000 minimum ERASE cycles per block
  • Data retention: 20 years (TYP)
• 65nm multilevel cell (MLC) process technology Package
  • 56-pin TSOP, 14 x 20mm
  • 64-ball fortified BGA, 13 x 11mm
• Green packages available
  • RoHS-compliant
  • Halogen-free
• Operating temperature
  • Ambient: –40°C to +85°C