NOR Flash Parallel 3V/3.3V 32Mbit 4M/2M x 8bit/16bit 70ns 48-Pin TSOP Tray

The M29EW is an asynchronous, parallel NOR Flash memory device manufactured on 65nm single-bit cell (SBC) technology. READ, ERASE, and PROGRAM operations are performed using a single low-voltage supply. Upon power-up, the device defaults to read array mode. The main memory array is divided into uniform blocks that can be erased independently so that valid data can be preserved while old data is purged. PROGRAM and ERASE commands are written to the command interface of the memory. An on-chip program/ erase controller simplifies the process of programming or erasing the memory by taking care of all special operations required to update the memory contents. The end of a PROGRAM or ERASE operation can be detected and any error condition can be identified. The command set required to control the device is consistent with JEDEC standards. CE#, OE#, and WE# control the bus operation of the device and enable a simple connection to most microprocessors, often without additional logic. The M29EW supports asynchronous random read and page read from all blocks of the array. It also features an internal program buffer that improves throughput by programming 256 words via one command sequence. The device contains a 128-word extended memory block which overlaps addresses with array block 0. The user can program this additional space and then protect it to permanently secure the contents. The device also features different levels of hardware and software protection to secure blocks from unwanted modification.

• Supply voltage
  • VCC = 2.7-3.6V (program, erase, read)
  • VCCQ = 1.65-3.6V (I/O buffers)
• Asynchronous random or page read
  • Page size: 8 words or 16 bytes
  • Page access: 25ns
  • Random access (VCCQ = 2.7-3.6V): 60ns (BGA); 70ns (TSOP)
• Buffer program: 256-word MAX program buffer
• Program time
  • 0.56µs per byte (1.8 MB/s TYP when using 256- word buffer size in buffer program without VPPH)
  • 0.31µs per byte (3.2 MB/s TYP when using 256- word buffer size in buffer program with VPPH)
• Memory organization
  • 32Mb: 64 main blocks, 64KB each, or eight 8KB boot blocks (top or bottom) and 63 main blocks, 64KB each
  • 64Mb: 128 main blocks, 64KB each, or eight 8KB boot blocks (top or bottom) and 127 main blocks, 64 KB each
  • 128Mb: 128 main blocks, 128KB each
• Program/erase controller
  • Embedded byte/word program algorithms
• Program/erase suspend and resume capability
  • READ operation on another block during a PROGRAM SUSPEND operation
  • READ or PROGRAM operation on one block during an ERASE SUSPEND operation on another block
• BLANK CHECK operation to verify an erased block
• Unlock bypass, block erase, chip erase, and write to buffer capability
  • Fast buffered/batch programming
  • Fast block and chip erase
• VPP/WP# pin protection
  • VPPH voltage on VPP to accelerate programming performance
  • Protects highest/lowest block (H/L uniform) or top/bottom two blocks (T/B boot)
• Software protection
  • Volatile protection
  • Nonvolatile protection
  • Password protection
  • Password access
• Extended memory block
  • 128-word (256-byte) block for permanent secure identification
  • Program or lock implemented at the factory or by the customer
• Low-power consumption: Standby mode
• JESD47H-compliant
  • 100,000 minimum ERASE cycles per block
  • Data retention: 20 years (TYP)
• 65nm single-bit cell process technology
• Packages (JEDEC-standard)
  • 56-pin TSOP (128Mb, 64Mb)
  • 48-pin TSOP (64Mb, 32Mb)
  • 64-ball FBGA (128Mb, 64Mb)
  • 48-ball BGA (64Mb, 32Mb)
• Green packages available
  • RoHS-compliant
  • Halogen-free
• Operating temperature
  • Ambient: -40°C to +85°C