SERIAL NOR, QUAD I/O, 128MB

The N25Q128 is a 128 Mbit (16Mb x 8) serial Flash memory, with advanced write protection mechanisms. It is accessed by a high speed SPI-compatible bus and features the possibility to work in XIP (“eXecution in Place”) mode. The N25Q128 supports innovative, high-performance quad/dual I/O instructions, these new instructions allow to double or quadruple the transfer bandwidth for read and program operations.Furthermore the memory can be operated with 3 different protocols:. Standard SPI (Extended SPI protocol). Dual I/O SPI. Quad I/O SPI. The Standard SPI protocol is enriched by the new quad and dual instructions (Extended SPI protocol). For Dual I/O SPI (DIO-SPI) all the instructions codes, the addresses and the data are always transmitted across two data lines. For Quad I/O SPI (QIO-SPI) the instructions codes, the addresses and the data are always transmitted across four data lines thus enabling a tremendous improvement in both random access time and data throughput.The memory can work in “XIP mode”, that means the device only requires the addresses and not the instructions to output the data. This mode dramatically reduces random access time thus enabling many applications requiring fast code execution without shadowing the memory content on a RAM. The XIP mode can be used with QIO-SPI, DIO-SPI, or Extended SPI protocol, and can be entered and exited using different dedicated instructions to allow maximum flexibility: for applications required to enter in XIP mode right after power up of the device, this can be set as default mode by using dedicated Non Volatile Register (NVR) bits. It is also possible to reduce the power on sequence time with the Fast POR (Power on Reset) feature, enabling a reduction of the latency time before the first read instruction can be performed.Another feature is the ability to pause and resume program and erase cycles by using dedicated Program/Erase Suspend and Resume instructions. The N25Q128 memory offers the following additional Features to be configured by using the Non Volatile Configuration Register (NVCR) for default /Non-Volatile settings or by using the Volatile and Volatile Enhanced Configuration Registers for Volatile settings:. the number of dummy cycles for fast read instructions (single, dual and, quad I/O) according to the operating frequency. the output buffer impedance. the type of SPI protocol (extended SPI, DIO-SPI or QIO-SPI). the required XIP mode. Fast or standard POR sequence. the Hold (Reset) functionality enabling/disabling.The memory is organized as 248 (64-Kbyte) main sectors, in products with Bottom or Top architecture there are 8 64-Kbyte boot sectors, and each boot sector is further divided into 16 4-Kbyte subsectors (128 subsectors in total). The boot sectors can be erased a 4-Kbyte subsector at a time or as a 64-Kbyte sector at a time. The entire memory can be also erased at a time or by sector.The memory can be write protected by software using a mix of volatile and non-volatile protection features, depending on the application needs. The protection granularity is of 64- Kbyte (sector granularity) for volatile protections. The N25Q128 has 64 one-time-programmable bytes (OTP bytes) that can be read and programmed using two dedicated instructions, Read OTP (ROTP) and Program OTP (POTP), respectively. These 64 bytes can be permanently locked by a particular Program OTP (POTP) sequence. Once they have been locked, they become read-only and this state cannot be reversed.

• SPI-compatible serial bus interface
• 108 MHz (maximum) clock frequency
• 2.7 V to 3.6 V single supply voltage
• Supports legacy SPI protocol and new Quad I/O or Dual I/O SPI protocol
• Quad/Dual I/O instructions resulting in an equivalent clock frequency up to 432 MHz:
• XIP mode for all three protocols
  • Configurable via volatile or non-volatile registers: enables XiP mode directly after power on
• Program/Erase suspend instructions
• Continuous read (entire memory) via single instruction:
  • Fast Read
  • Quad or Dual Output Fast Read
  • Quad or Dual I/O Fast Read
• Flexible to fit application:
  • Configurable number of dummy cycles
  • Output buffer configurable
  • Fast POR instruction: decrease power-on time
  • Reset function (upon customer request)
• 64-byte user-lockable, one-time programmable (OTP) area
• Erase capability
  • Subsector (4-Kbyte) granularity in the 8 boot sectors (bottom or top parts)
  • Sector (64-Kbyte) granularity
• Write protections
  • Software write protection applicable to every 64-Kbyte sector (volatile lock bit)
  • Hardware write protection: protected area size defined by non-volatile bits (BP0, BP1, BP2, BP3 and TB bit)
  • Additional smart protections available upon customer request
• Electronic signature
  • JEDEC standard two-byte signature (BA18h)
  • Additional 2 Extended Device ID (EDID) bytes to identify device factory options
  • Unique ID code (UID) with 14 bytes read-only, available upon customer request
• More than 100,000 program/erase cycles per sector
• More than 20 years data retention
• Packages (all packages RoHS compliant)
  • F8 = VDFPN8 8 x 6 mm (MLP8)
  • 12 = TBGA24 6 x 8 mm
  • F6 = VDFPN8 6 x 5 mm (MLP)
  • SF = SO16 (300 mils body width)
  • SE = SO8W (SO8 208 mils body width)