Описание
The LPC435x/3x/2x/1x are ARM Cortex-M4 based microcontrollers for embedded applications which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI), advanced configurable peripherals such as the State Configurable Timer (SCT) and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals. The LPC435x/3x/2x/1x operate at CPU frequencies of up to 204 MHz. The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point unit is integrated in the core. The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which is upward code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor, designed as a replacement for existing 8/16-bit microcontrollers, offers up to 204 MHz performance with a simple instruction set and reduced code size.
- Cortex-M4 Processor core
- ARM Cortex-M4 processor, running at frequencies of up to 204 MHz
- ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions
- ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC)
- Hardware floating-point unit
- Non-maskable Interrupt (NMI) input
- JTAG and Serial Wire Debug (SWD), serial trace, eight break points, and four watchpoints
- Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support
- System tick timer
- Cortex-M0 Processor core
- ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4 application processor
- Running at frequencies of up to 204 MHz
- JTAG
- Built-in NVIC
- On-chip memory
- Up to 1 MB on-chip dual bank flash memory with flash accelerator
- 16 kB on-chip EEPROM data memory
- 136 kB SRAM for code and data use
- Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually
- 64 kB ROM containing boot code and on-chip software drivers
- 64 bit of general-purpose One-Time Programmable (OTP) memory
- Configurable digital peripherals
- Serial GPIO (SGPIO) interface
- State Configurable Timer (SCT) subsystem on AHB
- Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, SCT, and ADC0/1
- Serial interfaces
- Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second
- 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2)
- One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY
- One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY
- USB interface electrical test software included in ROM USB stack
- One 550 UART with DMA support and full modem interface
- Three 550 USARTs with DMA and synchronous mode support and a smart card interface conforming to ISO7816 specification. One USART with IrDA interface
- Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge
- Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support
- One SPI controller
- One Fast-mode Plus I²C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I²C-bus specification. Supports data rates of up to1 Mbit/s
- One standard I²C-bus interface with monitor mode and with standard I/O pins
- Two I²S interfaces, each with DMA support and with one input and one output
- Digital peripherals
- External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices
- Secure Digital Input Output (SD/MMC) card interface
- Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves
- Up to 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors
- GPIO registers are located on the AHB for fast access. GPIO ports have DMA support
- Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources
- Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins
