Description
The TMS470R1A64 (2) device is a member of the Texas Instruments TMS470R1x family of general-purpose 16/32-bit reduced instruction set computer (RISC) microcontrollers. The A64 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining high code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from 0. The TMS470R1A64 utilizes the big-endian format, where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte.High-end embedded control applications demand more performance from their controllers while maintaining low costs. The A64 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.The A64 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.The flash memory on the A64 device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz. In pipeline mode, the flash operates with a system clock frequency of up to 48 MHz.The A64 device has six communication interfaces: two SPIs, two SCIs, an SCC, and a C2SIa. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIa allows the A64 to transmit and receive messages on a class II network following an SAE J1850 (3) standard.
- 24-MHz System Clock (48-MHz Pipeline Mode)
- Independent 16/32-Bit Instruction Set
- Open Architecture With Third-Party Support
- Built-In Debug Module
- Big-Endian Format Utilized
- 64K-Byte Program Flash
- One Bank With Five Contiguous Sectors
- Internal State Machine for Programming and Erase
- 8K-Byte Static RAM (SRAM)
- Core Supply Voltage (VCC): 1.71 V-2.06 V
- I/O Supply Voltage (VCCIO): 3.0 V-3.6 V
- Low-Power Modes: STANDBY and HALT
- Extended Industrial Temperature Range
- 32-Bit Address Space Decoding
- Bus Supervision for Memory and Peripherals
- Analog Watchdog (AWD) Timer
- Real-Time Interrupt (RTI)
- System Integrity and Failure Detection
- Multiply-by-4 or -8 Internal ZPLL Option
- ZPLL Bypass Mode
- Two Serial Peripheral Interfaces (SPIs)
- 255 Programmable Baud Rates
- Two Serial Communication Interfaces (SCIs)
- 224 Selectable Baud Rates
- Asynchronous/Isosynchronous Modes
- Standard CAN Controller (SCC)
- 16-Mailbox Capacity
- Fully Compliant With CAN Protocol, Version 2.0B
- Class II Serial Interface (C2SIa)
- Two Selectable Data Rates
- Normal Mode 10.4 Kbps and 4X Mode 41.6 Kbps
- 13 Programmable I/O Channels:
- 12 High-Resolution Pins
- 1 Standard-Resolution Pin
- High-Resolution Share Feature (XOR)
- HET RAM (64-Instruction Capacity)
- 64-Word FIFO Buffer
- Single- or Continuous-Conversion Modes
- 1.55 µs Minimum Sample and Conversion Time
- Calibration Mode and Self-Test Features
- Programmable Low-Frequency External Clock (CLK)