Описание
The AT91M42800A is a member of the AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91 ARM-based MCU family also features ’s high-density, in system programmable, nonvolatile memory technology. The AT91M42800A has a direct connection to off-chip memory, including Flash, through the External Bus Interface. The Power Management Controller allows the user to adjust device activity according to system requirements, and, with the 32.768 kHz low-power oscillator, enables the AT91M42800A to reduce power requirements to an absolute minimum. The AT91M42800A is manufactured using ’s high-density CMOS technology. By combining the ARM7TDMI processor core with on chip SRAM and a wide range of peripheral functions including timers, serial communication controllers and a versatile clock generator on a monolithic chip, the AT91M42800A provides a highly-flexible and cost-effective solution to many compute-intensive applications.
- Utilizes the ARM7TDMI® ARM® Thumb® Processor Core
- High-performance 32-bit RISC Architecture
- High-density 16-bit Instruction Set
- Leader in MIPS/Watt
- Embedded ICE (In-circuit Emulation)
- 8K Bytes Internal SRAM
- Fully Programmable External Bus Interface (EBI)
- Maximum External Address Space of 64M Bytes
- Up to 8 Chip Selects
- Software Programmable 8/16-bit External Data Bus
- 8-channel Peripheral Data Controller
- 8-level Priority, Individually Mask able, Vectored Interrupt Controller
- 5 External Interrupts, Including a High-priority, Low-latency Interrupt Request
- 54 Programmable I/O Lines
- 6-channel 16-bit Timer/Counter
- 6 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel
- 2 USARTs
- 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
- Support for up to 9-bit Data Transfers
- 2 Master/Slave SPI Interfaces
- 2 Dedicated Peripheral Data Controller (PDC) Channels per SPI
- 8- to 16-bit Programmable Data Length
- 4 External Slave Chip Selects per SPI
